CS42L52 Datasheet, PDF (47/82 Pages) Cirrus Logic – Low Power, Stereo CODEC w/Headphone & Speaker Amps

6.6.5
CS42L52
DAC Interface Format
Configures the digital interface format for data on SDIN.
DACDIF[1:0]
00
01
10
11
Application:
DAC Interface Format
Left Justified, up to 24-bit data
I²S, up to 24-bit data
Right Justified
Reserved
“Digital Interface Formats” on page 36
Note: Select the audio word length for Right Justified using the AWL[1:0] bits (“Audio Word Length” on
page 47).
6.6.6
Audio Word Length
Configures the audio sample word length used for the data into SDIN and out of SDOUT.
AWL[1:0]
00
01
10
11
Application:
Audio Word Length
DSP Mode
32-bit data
24-bit data
20-bit data
16-bit data
“DSP Mode” on page 36
Right Justified (DAC ONLY)
24-bit data
20-bit data
18-bit data
16-bit data
Note: When the internal MCLK/LRCK ratio is set to 125 in master mode, the 32-bit data width option
for DSP Mode is not valid unless SCLK=MCLK.
6.7 Interface Control 2 (Address 07h)
7
6
5
Reserved SCLK=MCLK DIGLOOP
4
3ST_SP
3
INV_SWCH
2
BIASLVL2
1
BIASLVL1
0
BIASLVL0
6.7.1
SCLK equals MCLK
Configures the SCLK signal source for master mode.
SCLK=MCLK
0
1
Output SCLK
Re-timed signal, synchronously derived from MCLK
Non-retimed, MCLK signal
Note: This bit is only valid for MCLK = 12.0000 MHz.
6.7.2
SDOUT to SDIN Digital Loopback
Configures an internal loops the signal on the SDOUT pin to SDIN.
DIGLOOP
0
1
Internal Loopback
Disabled; SDOUT internally disconnected from SDIN
Enabled; SDOUT internally connected to SDIN
DS680A1
47