CS42L52 Datasheet, PDF (44/82 Pages) Cirrus Logic – Low Power, Stereo CODEC w/Headphone & Speaker Amps

CS42L52
6.4 Power Control 3 (Address 04h)
7
6
5
4
PDN_HPB1 PDN_HPB0 PDN_HPA1 PDN_HPA0
3
2
1
0
PDN_SPKB1 PDN_SPKB0 PDN_SPKA1 PDN_SPKA0
6.4.1
Headphone Power Control
Configures how the SPK/HP_SW pin, 6, controls the power for the headphone amplifier.
PDN_HPx[1:0]
00
01
10
11
Headphone Status
Headphone channel is ON when the SPK/HP_SW pin, 6, is LO.
Headphone channel is OFF when the SPK/HP_SW pin, 6, is HI.
Headphone channel is ON when the SPK/HP_SW pin, 6, is HI.
Headphone channel is OFF when the SPK/HP_SW pin, 6, is LO.
Headphone channel is always ON.
Headphone channel is always OFF.
6.4.2
Speaker Power Control
Configures how the SPK/HP_SW pin, 6, controls the power for the speaker amplifier.
PDN_SPKx[1:0]
00
01
10
11
Speaker Status
Speaker channel is ON when the SPK/HP_SW pin, 6, is LO.
Speaker channel is OFF when the SPK/HP_SW pin, 6, is HI.
Speaker channel is ON when the SPK/HP_SW pin, 6, is HI.
Speaker channel is OFF when the SPK/HP_SW pin, 6, is LO.
Speaker channel is always ON.
Speaker channel is always OFF.
6.5 Clocking Control (Address 05h)
7
AUTO
6
SPEED1
5
SPEED0
4
32k_GROUP
3
VIDEOCLK
2
RATIO1
1
RATIO0
0
MCLKDIV2
6.5.1
Auto-Detect
Configures the auto-detect circuitry for detecting the speed mode of the CODEC when operating as a
slave.
AUTO
0
1
Application:
Auto-detection of Speed Mode
Disabled
Enabled
“Serial Port Clocking” on page 34
Notes:
1. The SPEED[1:0] bits are ignored and speed is determined by the MCLK/LRCK ratio.
2. When AUTO is disabled and the CODEC operates in master mode, the MCLKDIV2 bit is ignored.
3. Certain sample and MCLK frequencies require setting the SPEED[1:0] bits, the 32k_GROUP bit
(“32kHz Sample Rate Group” on page 45) and/or the VIDEOCLK bit (“27 MHz Video Clock” on
page 45) and RATIO[1:0] bits (“Internal MCLK/LRCK Ratio” on page 45). Low sample rates may also
affect dynamic range performance in the typical audio band. Refer to the referenced application for
more information.
44
DS680A1