CS42L52 Datasheet, PDF (30/82 Pages) Cirrus Logic – Low Power, Stereo CODEC w/Headphone & Speaker Amps

CS42L52
SPKAMUTE
SPKBMUTE
MUTE50/50
SPKMONO
SPKSWAP
SPKB=A
SPKAVOL[7:0]
SPKBVOL[7:0]
+0dB/-102dB
0.5dB steps
BATTCMP
VPREF[3:0]
VPLVL[7:0]
Battery
Compensation
THRFLD
SPKATTN[2:0]
Thermal
Foldback
TWRN
TERR
Thermal
Monitor
from DSP
Engine
VOL
PWM
Modulator
Gate
Drive
PDN_SPKA[1:0]
PDN_SPKB[1:0]
RELEASE
SPKASHRT
SPKBSHRT
Short
Circuit
Figure 11. PWM Output Stage
+
-
A
+
-
B
Speaker
Outputs
HPAMUTE
HPBMUTE
HPA_VOL[7:0]
HPB_VOL[7:0]
+0dB/-102dB
0.5dB steps
PDN_HPA[1:0]
PDN_HPB[1:0]
HPGAIN[2:0]
from DSP
Engine
VOL
DAC
Analog Passthru
from PGA
VOL
PASSAMUTE
PASSBMUTE
PASSAVOL[7:0]
PASSBVOL[70]
+12dB/-60dB
0.5dB steps
(uses PGA)
PASSTHRUA
PASSTHRUB
Charge
Pump
CHGFREQ[3:0]
A
HP/Line
Outputs
B
Figure 12. Analog Output Stage
Referenced Control Register Location
PWM Control
SPKxMUTE ......................... “Speaker Mute” on page 53
MUTE50/50 ......................... “Speaker Mute 50/50 Control” on page 54
SPKMONO .......................... “Speaker MONO Control” on page 54
SPKxVOL[7:0] ..................... “Speaker Volume Control” on page 64
SPKSWAP........................... “Speaker Channel Swap” on page 54
SPKB=A .............................. “Speaker Volume Setting B=A” on page 54
BATTCMP ........................... “Battery Compensation” on page 71
VPREF[3:0] ......................... “VP Reference” on page 72
VPLVL[7:0] .......................... “VP Voltage Level (Read Only)” on page 72
THRFLD .............................. “Thermal Foldback” on page 73
SPKATTN[2:0] ..................... “Speaker Attenuation” on page 74
PDN_SPKx[1:0]................... “Speaker Power Control” on page 44
RELEASE............................ “Temperature Acknowledge & Release” on page 73
TWRN.................................. “Thermal Warning Status (Read Only)” on page 73
TERR................................... “Thermal Error Status (Read Only)” on page 73
SPKxSHRT.......................... “Speaker Current Load Status (Read Only)” on page 72
Referenced Control Register Location
Analog Output
HPxMUTE ........................... “Headphone Mute” on page 53
HPxVOL[7:0] ....................... “Headphone Volume Control” on page 63
PDN_HPx[1:0] ..................... “Headphone Power Control” on page 44
HPGAIN[2:0]........................ “Headphone Analog Gain” on page 51
PASSTHRUx ....................... “Passthru Analog” on page 52
PASSxMUTE ....................... “Passthru Mute” on page 52
PASSxVOL[7:0] ................... “Passthru x Volume” on page 56
CHGFREQ .......................... “Charge Pump Frequency” on page 74
4.3.1
Beep Generator
The Beep Generator generates audio frequencies across approximately two octave major scales. It offers
three modes of operation: Continuous, multiple and single (one-shot) beeps. Sixteen on and eight off
times are available.
Note: The Beep is generated before the limiter and may affect desired limiting performance. If the lim-
iter function is used, it may be required to set the beep volume sufficiently below the threshold to prevent
the peak detect from triggering. Since the master volume control, MSTxVOL[7:0], will affect the beep vol-
ume, DAC volume may alternatively be controlled using the PMIXxVOL[6:0] bits.
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DS680A1