CS42L52 Datasheet, PDF (48/82 Pages) Cirrus Logic – Low Power, Stereo CODEC w/Headphone & Speaker Amps

6.7.3
CS42L52
Tri-State Serial Port Interface
Determines the state of the serial port drivers.
3ST_SP
0
1
Serial Port Status
Slave Mode
Serial Port clocks are inputs and SDOUT is output
Serial Port clocks are inputs and SDOUT is HI-Z
Master Mode
Serial Port clocks and SDOUT are outputs
Serial Port clocks and SDOUT are HI-Z
Notes:
1. Slave/Master Mode is determined by the M/S bit in “Master/Slave Mode” on page 46.
2. When the serial port is tri-stated in master mode, the ADC and DAC serial ports are clocked internally.
6.7.4
Speaker/Headphone Switch Invert
Determines the control signal polarity of the SPK/HP_SW pin.
INV_SWCH
0
1
SPK/HP_SW pin 6 Control
Not inverted
Inverted
6.7.5
MIC Bias Level
Sets the output voltage level on the MICBIAS output pin.
BIASLVL[2:0]
000
001
010
011
100
101
110
111
Output Bias Level
0.5 x VA
0.6 x VA
0.7 x VA
0.8 x VA
0.83 x VA
0.91 x VA
Reserved
Reserved
6.8 Input x Select: ADCA and PGAA (Address 08h), ADCB and PGAB (Address 09h)
7
6
5
ADCASEL2 ADCASEL1 ADCASEL0
4
PGAASEL5
3
2
1
0
PGAASEL4 PGAASEL3 PGAASEL2 PGAASEL1
6.8.1
ADC Input Select
Selects the specified analog input signal into ADCx.
ADCxSEL[2:0]
000
001
010
011
100
101
110
111
Application:
Selected Input to ADCx
AIN1x
AIN2x
AIN3x
AIN4x
PGAx - Use PGAxSEL bits (“PGA Input Mapping” on page 49) to select input channels
Reserved
Reserved
Reserved
“Analog Inputs” on page 26
48
DS680A1