CS42L52 Datasheet, PDF (34/82 Pages) Cirrus Logic – Low Power, Stereo CODEC w/Headphone & Speaker Amps

CS42L52
4.5.2.1 Maintaining a Desired Output Level
Using SPKxVOL, the speaker output level must first be attenuated by the decibel equivalent of the expect-
ed VP supply range (MAX relative to MIN). The CS42L52 then gradually reduces the attenuation as the
VP supply drops from it’s maximum level, maintaining a nearly constant power output.
Compensation Example 1 (VP Battery supply ranges from 4.5 V to 3.0 V)
1. Set speaker attenuation (SPKxVOL) to -3.5 dB. The VP supply changes ~3.5 dB.
2. Set the reference VP supply (VPREF) to 4.5 V.
3. Enable battery compensation (BATTCMP).
The CS42L52 automatically adjusts the output level as the battery discharges.
Compensation Example 2 (VP Battery supply ranges from 5.0 V to 1.6 V)
1. Set speaker attenuation (SPKxVOL) to -10 dB. The VP supply changes ~9.9 dB.
2. Set the reference VP supply (VPREF) to 5.0 V.
3. Enable battery compensation (BATTCMP).
The CS42L52 automatically adjusts the output level as the battery discharges. Refer to Figure 15 on page
34. In this example, the VP supply changes over a wide range, illustrating the accuracy of the CS42L52’s
battery compensation.
-6
Battery Compensated
-8
PWM Output Level
-10
-12
Uncompensated
-14
PWM Output
-16
Level
-18
-20
-22
-24
4.9 4.6 4.3
4
3.7 3.4 3.1 2.8 2.5 2.2 1.9 1.6
VP Supply (V)
Figure 15. Battery Compensation
Referenced Control
Register Location
VPREF ................................ “VP Reference” on page 72
SPKxVOL ............................ “Speaker Volume Control” on page 64
4.6 Serial Port Clocking
The CODEC serial audio interface port operates either as a slave or master, determined by the M/S bit. It
accepts externally generated clocks in Slave Mode and will generate synchronous clocks derived from an
input master clock (MCLK) in Master Mode. Refer to the tables below for the required setting in register 05h
and 06h associated with a given MCLK and sample rate.
Referenced Control Register Location
M/S
Register 05h
Register 06h
“Master/Slave Mode” on page 46
“Clocking Control (Address 05h)” on page 44
“Interface Control 1 (Address 06h)” on page 46
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DS680A1