CS42L52 Datasheet, PDF (46/82 Pages) Cirrus Logic – Low Power, Stereo CODEC w/Headphone & Speaker Amps

6.5.6
CS42L52
MCLK Divide By 2
Divides the input MCLK by 2 prior to all internal circuitry.
MCLKDIV2
0
1
Application:
MCLK signal into CODEC
No divide
Divided by 2
“Serial Port Clocking” on page 34
Note: In slave mode, this bit is ignored when the AUTO bit (“Auto-Detect” on page 44) is disabled.
6.6 Interface Control 1 (Address 06h)
7
6
5
M/S
INV_SCLK
ADCDIF
4
DSP
3
DACDIF1
2
DACDIF0
1
AWL1
0
AWL0
6.6.1
Master/Slave Mode
Configures the serial port I/O clocking.
M/S
Serial Port Clocks
0
Slave (input ONLY)
1
Master (output ONLY)
6.6.2
SCLK Polarity
Configures the polarity of the SCLK signal.
INV_SCLK
0
1
SCLK Polarity
Not Inverted
Inverted
6.6.3
ADC Interface Format
Configures the digital interface format for data on SDOUT.
ADCDIF
0
1
Application:
ADC Interface Format
Left Justified
I²S
“Digital Interface Formats” on page 36
6.6.4
DSP Mode
Configures a data-packed interface format for both the ADC and DAC.
DSP
0
1
Application:
DSP Mode
Disabled
Enabled
“DSP Mode” on page 36
Notes:
1. Select the audio word length using the AWL[1:0] bits (“Audio Word Length” on page 47).
2. The interface format for both the ADC and the DAC must be set to “Left-Justified” when DSP Mode
is enabled.
46
DS680A1