CS42L52 Datasheet, PDF (45/82 Pages) Cirrus Logic – Low Power, Stereo CODEC w/Headphone & Speaker Amps

6.5.2
CS42L52
Speed Mode
Configures the speed mode of the CODEC in slave mode and sets the appropriate MCLK divide ratio for
LRCK and SCLK in master mode.
SPEED[1:0]
00
01
10
11
Application:
Slave Mode
Serial Port Speed
Double-Speed Mode (DSM - 50 kHz -100 kHz Fs)
Single-Speed Mode (SSM - 4 kHz -50 kHz Fs)
Half-Speed Mode (HSM - 12.5kHz -25 kHz Fs)
Quarter-Speed Mode (QSM - 4 kHz -12.5 kHz Fs)
“Serial Port Clocking” on page 34
Master Mode
MCLK/LRCK Ratio
512
256
128
128
SCLK/LRCK Ratio
64
64
64
64
Notes:
1. Slave/Master Mode is determined by the M/S bit in “Master/Slave Mode” on page 46.
2. Certain sample and MCLK frequencies require setting the SPEED[1:0] bits, the 32k_GROUP bit
(“32kHz Sample Rate Group” on page 45) and/or the VIDEOCLK bit (“27 MHz Video Clock” on
page 45) and RATIO[1:0] bits (“Internal MCLK/LRCK Ratio” on page 45). Low sample rates may also
affect dynamic range performance in the typical audio band. Refer to the referenced application for
more information.
3. These bits are ignored when the AUTO bit (“Auto-Detect” on page 44) is enabled.
6.5.3
32kHz Sample Rate Group
Specifies whether or not the input/output sample rate is 8 kHz, 16 kHz or 32 kHz.
32kGROUP
0
1
Application:
8 kHz, 16 kHz or 32 kHz sample rate?
No
Yes
“Serial Port Clocking” on page 34
6.5.4
27 MHz Video Clock
Specifies whether or not the external MCLK frequency is 27 MHz
VIDEOCLK
0
1
Application:
27 MHz MCLK?
No
Yes
“Serial Port Clocking” on page 34
6.5.5
Internal MCLK/LRCK Ratio
Configures the internal MCLK/LRCK ratio.
RATIO[1:0]
00
01
10
11
Application:
Internal MCLK Cycles per LRCK
128
125
132
136
“Serial Port Clocking” on page 34
SCLK/LRCK Ratio in Master Mode
64
62
66
68
DS680A1
45