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CS42L52 Datasheet, PDF (26/82 Pages) Cirrus Logic – Low Power, Stereo CODEC w/Headphone & Speaker Amps | |||
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4.2 Analog Inputs
CS42L52
D IG M IX
D IG SU M [1:0]
Swap/
Mix
ADCAMUTE
DIGSFT
DIGZC
ADCAVOL[7:0]
+24/-96dB
1dB steps
HPFRZA
HPFA
HPFA_CF[1:0]
Gain Adjust
PDN_ADCA
INV_ADCA
PDN_CHRG
ADC
ALCA
ALCASRDIS
ALCAZCDIS
ALCARATE[5:0]
ALCRRATE[5:0]
MAX[2:0]
M IN [2:0 ]
ALC
ALCB
ALCBSRDIS
ALCBZCDIS
ADCASEL[2:0]
No`ise Gate
NGALL
NG
THRESH[3:0]
NGDELAY[1:0]
ADCBSEL[2:0]
Gain Adjust
ADCBMUTE
DIGSFT
DIGZC
ADCBVOL[7:0]
+24/-96dB
1dB steps
HPFRZB
HPB
HPFB_CF[1:0]
ADC
PDN_ADCB
INV_ADCB
PDN_CHRG
= PGAASEL[5:1]
Σ
PDN_PGAA
PGAAVOL[5:0]
ADCB=A
ANLGSFTA
ANLGZCA
PDN_PGAB
PGABVOL[5:0]
ADCB=A
ANLGSFTB
ANLGZCB
Refer to
âMIC Inputsâ
BIASLVL[2:0]
PDN_BIAS
Refer to
âMIC Inputsâ
Σ
= PGABSEL[5:1]
AIN1A
AIN2A
AIN3A/MIC1-/
MIC1A
AIN4A/ MIC1+/
MIC2A
MICBIAS
AIN4B/ MIC2+/
MIC2B
AIN3B/MIC2-/
MIC1B
AIN2B
AIN1B
TO DSP Engine
FROM DSP ENGINE
Figure 5. Analog Input Signal Flow
ANALOG PASS THRU TO
HEADPHONE AMPLIFIER MUX
Referenced Control
Register Location
Analog Front End
PDN_PGAx .........................
PGAxVOL[5:0] .....................
ADCB=A ..............................
ANLGSFTx ..........................
ANLGZCx ............................
ADCxSEL[2:0] .....................
PGAxSEL5,4,3,2,1 ..............
BIASLVL[2:0] .......................
PDN_BIAS...........................
PDN_ADCx .........................
PDN_CHRG ........................
INV_ADCx ...........................
HPFRZx...............................
HPFx ...................................
HPFx_CF[1:0]......................
ADCxOVFL..........................
Digital Volume
ADCxMUTE .........................
ADCxVOL ............................
ALCx....................................
ALCxSRDIS.........................
ALCxZCDIS .........................
ALCARATE[5:0]...................
ALCRRATE[5:0] ..................
MAX[2:0]..............................
MIN[2:0] ...............................
NGALL.................................
NG .......................................
THRESH[3:0].......................
NGDELAY[1:0] ....................
Miscellaneous
DIGSUM[1:0] .......................
DIGMUX ..............................
âPower Down PGAxâ on page 42
âPGAx Volumeâ on page 56
âADC Channel B=Aâ on page 50
âCh. x Analog Soft Rampâ on page 49
âCh. x Analog Zero Crossâ on page 49
âADC Input Selectâ on page 48
âPGA Input Mappingâ on page 49
âMIC Bias Levelâ on page 48
âPower Down MIC Biasâ on page 43
âPower Down ADCxâ on page 43
âPower Down ADC Charge Pumpâ on page 42
âInvert ADC Signal Polarityâ on page 50
âADCx High-Pass Filter Freezeâ on page 49
âADCx High-Pass Filterâ on page 49
âHPF x Corner Frequencyâ on page 50
âADCx Overflow (Read Only)â on page 71
âADC Muteâ on page 51
âADCx Volumeâ on page 57
âALCx Enableâ on page 67
âALCx Soft Ramp Disableâ on page 55
âALCx Zero Cross Disableâ on page 55
âALC Attack Rateâ on page 67
âALC Release Rateâ on page 68
âALC Maximum Thresholdâ on page 68
âALC Minimum Thresholdâ on page 69
âNoise Gate All Channelsâ on page 69
âNoise Gate Enableâ on page 69
âNoise Gate Threshold and Boostâ on page 70
âNoise Gate Delay Timingâ on page 70
âDigital Sumâ on page 50
âDigital MUXâ on page 50
26
DS680A1
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