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AM186ED Datasheet, PDF (82/88 Pages) Advanced Micro Devices – High Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges
Ready and Peripheral (20 MHz and 25 MHz)
Preliminary
Preliminary
Parameter
20 MHz
25 MHz
No. Symbol
Description
Min
Max
Min
Max Unit
Ready and Peripheral Timing Requirements
47
tSRYCL SRDY Transition Setup Time(a)
10
48
tCLSRY SRDY Transition Hold Time(a)
3
49
tARYCH ARDY Resolution Transition Setup Time(b)
10
50
tCLARX ARDY Active Hold Time(a)
4
10
ns
3
ns
10
ns
4
ns
51
tARYCHL ARDY Inactive Holding Time
6
6
ns
52
tARYLCL ARDY Setup Time(a)
15
15
ns
53
tINVCH Peripheral Setup Time(b)
10
10
ns
54
tINVCL
DRQ Setup Time(b)
10
10
ns
Peripheral Timing Responses
55
tCLTMV Timer Output Delay
25
20
ns
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions
are with CL =50 pF. For switching tests, VIL=0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V.
a This timing must be met to guarantee proper operation.
T b This timing must be met to guarantee recognition at the clock edge.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges
F Ready and Peripheral (33 MHz and 40 MHz)
Parameter
No. Symbol
Description
A Ready and Peripheral Timing Requirements
47
tSRYCL SRDY Transition Setup Time(a)
48
tCLSRY SRDY Transition Hold Time(a)
49
tARYCH ARDY Resolution Transition Setup Time(b)
R 50
tCLARX ARDY Active Hold Time(a)
51
tARYCHL ARDY Inactive Holding Time
52
tARYLCL ARDY Setup Time(a)
D53
tINVCH Peripheral Setup Time(b)
Preliminary
33 MHz
40 MHz
Min
Max
Min
Max Unit
8
5
ns
3
2
ns
8
5
ns
4
3
ns
6
5
ns
10
5
ns
8
5
ns
54
tINVCL
DRQ Setup Time(b)
8
5
ns
Peripheral Timing Responses
55
tCLTMV Timer Output Delay
15
12
ns
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions
are with CL =50 pF. For switching tests, VIL=0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V.
a This timing must be met to guarantee proper operation.
b This timing must be met to guarantee recognition at the clock edge.
82
Am186ED/EDLV Microcontrollers