AM186ED Datasheet, PDF (80/88 Pages) Advanced Micro Devices – High Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers

PRELIMINARY
SWITCHING CHARACTERISTICS over Commercial operating ranges
Clock (33 MHz and 40 MHz)
Preliminary
Parameter
33 MHz
40 MHz
No. Symbol
Description
Min
Max
Min
Max Unit
CLKIN Requirements
36
t_CKIN X1 Period^(a)
37
t_CLCK X1 Low Time (1.5 V)^(a)
38
t_CHCK X1 High Time (1.5 V)^(a)
39
t_CKHL X1 Fall Time (3.5 to 1.0 V)^(a)
40
t_CKLH X1 Rise Time (1.0 to 3.5 V)^(a)
CLKOUT Timing
30
60
25
60 ns
10
7.5
ns
10
7.5
ns
5
5 ns
5
5 ns
42
t_CLCL CLKOUTA Period
30
25
ns
43
t_CLCH CLKOUTA Low Time (C_L=50 pF) 0.5t_CLCL–1.5 =13.5
0.5t_CLCL–1.25 =11.25
ns
44
t_CHCL CLKOUTA High Time (C_L=50 pF) 0.5t_CLCL–1.5 =13.5
0.5t_CLCL–1.25 =11.25
ns
45 t_CH1CH2 CLKOUTA Rise Time (1.0 to 3.5 V)
3
3 ns
46
t_CL2CL1 CLKOUTA Fall Time (3.5 to 1.0 V)
3
3 ns
61
t_LOCK Maximum PLL Lock Time
1
1 ms
69
t_CICOA X1 to CLKOUTA Skew
15
15 ns
70
t_CICOB X1 to CLKOUTB Skew
25
25 ns
T _Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions
are with C_L =50 pF. For switching tests, V_IL=0.45 V and V_IH =2.4 V, except at X1 where V_IH =V_CC – 0.5 V.
a The specifications for CLKIN are applicable to the normal PLL and CLKDIV2 modes.
F _{The PLL should be used for operations from 16.667 MHz to 40 MHz. For operations below 16.667 MHz, the CLKDIV2}
mode should be used.
Because the CLKDIV2 input frequency is two times the system frequency, the specifications for twice the frequency should
D ^{R A used for CLKDIV2 mode. For example, use the 20 MHz CLKIN specifications for 10 MHz operation.}
80
Am186ED/EDLV Microcontrollers