AM186ED Datasheet, PDF (28/88 Pages) Advanced Micro Devices – High Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers

PRELIMINARY
they overlap. The PCS signals take precedence over pullup or pulldown. The pins that are multiplexed with
DRAM accesses when DRAM and memory-mapped PIO31–PIO0 are listed in Table 2 and Table 3.
peripherals overlap.
After power-on reset, the PIO pins default to various
PCS5 is three-stated and held resistively High during a configurations. The column titled Power-On Reset
bus hold condition. In addition, PCS5 has a weak Status in Table 2 and Table 3 lists the defaults for the
internal pullup resistor that is active during reset.
PIOs. Most of the PIO pins are configured as PIO
Unlike the UCS and LCS chip selects, the PCS outputs
assert with the multiplexed AD address bus. Note also
that each peripheral chip select asserts over a 256-
inputs with pullup after power-on reset. The system
initialization code must reconfigure any PIO pins as
required.
byte address range, which is twice the address range The A19–A17 address pins default to normal operation
covered by peripheral chip selects in the 80C186 and on power-on reset, allowing the processor to correctly
80C188 microcontrollers. PCS5 also has extended begin fetching instructions at the boot address
wait state options.
FFFF0h. The DT/R, DEN, and SRDY pins also default
A1—When the EX bit in the MCS and PCS auxiliary
register is 0, this pin supplies an internally latched
address bit 1 to the system. During a bus hold
condition, A1 retains its previously latched value.
PCS6/A2/PIO2
Peripheral Chip Select 6 (output, synchronous)
Latched Address Bit 2 (output, synchronous)
PCS6—This pin indicates to the system that a memory
T ^{access is in progress to the seventh region of the}
peripheral memory block (either I/O or memory
address space). The base address of the peripheral
memory block is programmable.
F _{The PCS chip selects can overlap either block of}
DRAM. The PCS chip selects must have the same or
greater number of wait states as the bank of DRAM
they overlap. The PCS signals take precedence over
DRAM accesses when DRAM and memory-mapped
A _{peripherals overlap.}
PCS6 is three-stated and held resistively High during a
bus hold condition. In addition, PCS6 has a weak
internal pullup resistor that is active during reset.
R Unlike the UCS and LCS chip selects, the PCS outputs
assert with the multiplexed AD address bus. Note also
that each peripheral chip select asserts over a 256-
byte address range, which is twice the address range
D ^{covered by peripheral chip selects in the 80C186 and}
to normal operation on power-on reset. PIO15 and
PIO24 should be set to normal operation before
enabling either bank of DRAM. PIO25 should be set to
normal operation before enabling the upper bank of
DRAM.
RD
Read Strobe (output, synchronous, three-state)
RD—This pin indicates to the system that the
microcontroller is performing a memory or I/O read
cycle. RD is guaranteed to not be asserted before the
address and data bus is floated during the address-to-
data transition. RD floats during a bus hold condition.
RES
Reset (input, asynchronous, level-sensitive)
This pin requires the microcontroller to perform a reset.
When RES is asserted, the microcontroller
immediately terminates its present activity, clears its
internal logic, and transfers CPU control to the reset
address, FFFF0h.
RES must be held Low for at least 1 ms.
RES can be asserted asynchronously to CLKOUTA
because RES is synchronized internally. For proper
initialization, V_CC must be within specifications, and
CLKOUTA must be stable for more than four
CLKOUTA periods during which RES is asserted.
80C188 microcontrollers. PCS6 also has extended
The microcontroller begins fetching instructions
wait state options.
approximately 6.5 CLKOUTA periods after RES is
deasserted. This input is provided with a Schmitt
A2—When the EX bit in the MCS and PCS auxiliary
trigger to facilitate power-on RES generation via an RC
register is 0, this pin supplies an internally latched
network.
address bit 2 to the system. During a bus hold
condition, A2 retains its previously latched value.
PIO31–PIO0 (Shared)
Programmable I/O Pins (input/output,
asynchronous, open-drain)
The Am186ED/EDLV microcontrollers provide 32
individually programmable I/O pins. Each PIO can be
programmed with the following attributes: PIO function
(enabled/disabled), direction (input/output), and weak
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Am186ED/EDLV Microcontrollers