AM186ED Datasheet, PDF (24/88 Pages) Advanced Micro Devices – High Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers

PRELIMINARY
refresh requests in priority of activity requests received interrupt recognition, the requesting device must
by the processor.
continue asserting INT2 until the request is
For more information, see the HLDA pin description on
page 23.
acknowledged. INT2 becomes INTA0 when INT0 is
configured in cascade mode.
INT0
INTA0—When the microcontroller interrupt control unit
is operating in cascade mode, this pin indicates to the
Maskable Interrupt Request 0 (input,
system that the microcontroller needs an interrupt type
asynchronous)
to process the interrupt request on INT0. The
This pin indicates to the microcontroller that an
interrupt request has occurred. If the INT0 pin is not
masked, the microcontroller transfers program
peripheral issuing the interrupt request must provide
the microcontroller with the corresponding interrupt
type.
execution to the location specified by the INT0 vector in
PWD—If pulse width demodulation is enabled, PWD
the microcontroller interrupt vector table.
processes a signal through the Schmitt trigger. PWD is
Interrupt requests are synchronized internally and can
used internally to drive TIMERIN0 and INT2, and PWD
be edge-triggered or level-triggered. To guarantee
is inverted internally to drive TIMERIN1 and INT4. If
interrupt recognition, the requesting device must
INT2 and INT4 are enabled and timer 0 and timer 1 are
continue asserting INT0 until the request is
acknowledged.
INT1/SELECT
Maskable Interrupt Request 1 (input,
asynchronous)
Slave Select (input, asynchronous)
T _{INT1—This pin indicates to the microcontroller that an}
interrupt request has occurred. If INT1 is not masked,
the microcontroller transfers program execution to the
location specified by the INT1 vector in the
F _{microcontroller interrupt vector table.}
Interrupt requests are synchronized internally and can
be edge-triggered or level-triggered. To guarantee
interrupt recognition, the requesting device must
A continue asserting INT1 until the request is
acknowledged.
SELECT—When the microcontroller interrupt control
unit is operating as a slave to an external interrupt
controller, this pin indicates to the microcontroller that
R _{an interrupt type appears on the address and data bus.}
The INT0 pin must indicate to the microcontroller that
an interrupt has occurred before the SELECT pin
indicates to the microcontroller that the interrupt type
D ^{appears on the bus.}
properly configured, the pulse width of the alternating
PWD signal can be calculated by comparing the values
in timer 0 and timer 1.
In PWD mode, the signals TIMERIN0/PIO11,
TIMERIN1/PIO0, and INT4/PIO30 can be used as
PIOs. If they are not used as PIOs, they are ignored
internally. The level of INT2/INTA0/PWD/PIO31 is
reflected in the PIO data register for PIO31 as if it was
a PIO.
INT3/INTA1/IRQ
Maskable Interrupt Request 3
(input, asynchronous)
Interrupt Acknowledge 1 (output, synchronous)
Slave Interrupt Request (output, synchronous)
INT3—This pin indicates to the microcontroller that an
interrupt request has occurred. If the INT3 pin is not
masked, the microcontroller then transfers program
execution to the location specified by the INT3 vector in
the microcontroller interrupt vector table.
Interrupt requests are synchronized internally, and can
be edge-triggered or level-triggered. To guarantee
interrupt recognition, the requesting device must
continue asserting INT3 until the request is
acknowledged. INT3 becomes INTA1 when INT1 is
configured in cascade mode.
INT2/INTA0/PWD/PIO31
INTA1—When the microcontroller interrupt control unit
Maskable Interrupt Request 2 (input,
is operating in cascade mode, this pin indicates to the
asynchronous)
system that the microcontroller needs an interrupt type
Interrupt Acknowledge 0 (output, synchronous)
to process the interrupt request on INT1. The
Pulse Width Demodulator (input, Schmitt trigger)
peripheral issuing the interrupt request must provide
INT2—This pin indicates to the microcontroller that an
the microcontroller with the corresponding interrupt
interrupt request has occurred. If the INT2 pin is not
type.
masked, the microcontroller transfers program
execution to the location specified by the INT2 vector in
the microcontroller interrupt vector table.
IRQ—When the microcontroller interrupt control unit is
operating as a slave to an external master interrupt
controller, this pin lets the microcontroller issue an
Interrupt requests are synchronized internally and can
interrupt request to the external master interrupt
be edge-triggered or level-triggered. To guarantee
controller.
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Am186ED/EDLV Microcontrollers