AM186ED Datasheet, PDF (47/88 Pages) Advanced Micro Devices – High Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers

PRELIMINARY
20-bit Adder/Subtractor
20
Transfer Counter Ch. 1
Destination Address Ch. 1
Source Address Ch. 1
Transfer Counter Ch. 0
Destination Address Ch. 0
Source Address Ch. 0
Adder Control
Logic
Timer Request
DMA
Control
Logic
DRQ1/Serial Port
Request
Selection
Logic
DRQ0/Serial Port
Interrupt
Request
Channel Control Register 1
Channel Control Register 0
20
16
T _{Internal Address/Data Bus}
Figure 10. DMA Unit Block Diagram
F _{DMA Channel Control Registers}
Each DMA control register determines the mode of op-
eration for the particular DMA channel. The DMA con-
A trol registers specify the following:
n The mode of synchronization
n Whether bytes or words are transferred
n Whether an interrupt is generated after the last
R transfer
n Whether the DRQ pins are configured as INT pins
n Whether DMA activity ceases after a programmed
D^{number of DMA cycles}
DMA Priority
The DMA channels can be programmed so that one
channel is always given priority over the other, or they
can be programmed to alternate cycles when both
have DMA requests pending. DMA cycles always have
priority over internal CPU cycles except between
locked memory accesses or word accesses to odd
memory locations. However, an external bus hold
takes priority over an internal DMA cycle.
Because an interrupt request cannot suspend a DMA
operation and the CPU cannot access memory during
a DMA cycle, interrupt latency time suffers during se-
quences of continuous DMA cycles. An NMI request,
n The relative priority of the DMA channel with re-
however, causes all internal DMA activity to halt. This
spect to the other DMA channel
allows the CPU to respond quickly to the NMI request.
n Whether the source address is incremented, decre-
mented, or maintained constant after each transfer
ASYNCHRONOUS SERIAL PORTS
n Whether the source address addresses memory or
I/O space
n Whether the destination address is incremented,
decremented, or maintained constant after trans-
fers
The Am186ED/EDLV microcontrollers provide two in-
dependent asynchronous serial ports. These ports pro-
vide full-duplex, bidirectional data transfer using
several industry-standard communications protocols.
The serial ports can be used as sources or destinations
of DMA transfers.
n Whether the destination address addresses mem-
ory or I/O space
Am186ED/EDLV Microcontrollers
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