AM186ED Datasheet, PDF (40/88 Pages) Advanced Micro Devices – High Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers

PRELIMINARY
CLOCK AND POWER MANAGEMENT
The clock and power management unit of the
Am186ED/EDLV microcontrollers includes a phase-
locked loop (PLL) and a second programmable system
clock output (CLKOUTB).
the output of the amplifier and negatively affects the op-
eration of the clock generator. Values for the loading on
X1 and X2 must be chosen to provide the necessary
phase shift and crystal operation.
Phase-Locked Loop
Selecting a Crystal
In a traditional 80C186/188 microcontroller design, the
When selecting a crystal, the load capacitance should
crystal frequency is twice that of the desired internal
clock. Because of the PLL on the Am186ED/EDLV mi-
always be specified (C_L). This value can cause vari-
ance in the oscillation frequency from the desired spec-
crocontrollers, the internal clock generated by the
ified value (resonance). The load capacitance and the
Am186ED/EDLV microcontrollers (CLKOUTA) is the
loading of the feedback network have the following re-
same frequency as the crystal. The PLL takes the crys-
lationship:
tal inputs (X1 and X2) and generates a 45–55% (worst
case) duty cycle intermediate system clock of the same
frequency. This removes the need for an external 2x
C_L =
(C₁
(C₁
⋅ C₂)
+ C₂)
+
C_S
oscillator, reducing system cost. The PLL is reset dur-
ing power-on reset by an on-chip power-on reset
(POR) circuit.
Crystal-Driven Clock Source
The internal oscillator circuit of the Am186ED/EDLV
microcontrollers is designed to function with a parallel
resonant fundamental or third overtone crystal. Be-
T _{cause of the PLL, the crystal frequency should be}
equal to the processor frequency. Do not replace a
crystal with an LC or RC equivalent.
F ^{The X1 and X2 signals are connected to an internal in-}
verting amplifier (oscillator) that provides, along with
the external feedback loading, the necessary phase
shift (Figure 8). In such a positive feedback circuit, the
inverting amplifier has an output signal (X2) 180 de-
A ^{grees out of phase of the input signal (X1).}
The external feedback network provides an additional
180-degree phase shift. In an ideal system, the input to
X1 will have 360 or zero degrees of phase shift. The ex-
ternal feedback network is designed to be as close to
R _{ideal as possible. If the feedback network is not provid-}
D ^{ing necessary phase shift, negative feedback dampens}
where C_S is the stray capacitance of the circuit. Placing
the crystal and C_L in series across the inverting ampli-
fier and tuning these values (C₁, C₂) allows the crystal
to oscillate at resonance. This relationship is true for
both fundamental and third-overtone operation. Finally,
there is a relationship between C₁ and C₂. To enhance
the oscillation of the inverting amplifier, these values
need to be offset with the larger load on the output (X2).
Equal values of these loads tend to balance the poles
of the inverting amplifier.
The characteristics of the inverting amplifier set limits
on the following parameters for crystals:
ESR (Equivalent Series Resistance) ......60 Ω max
Drive Level ..............................................1 mW max
The recommended range of values for C₁ and C₂ are
as follows:
C₁ ..................................................................15 pF ± 20%
C₂ ..................................................................22 pF ± 20%
The specific values for C₁ and C₂ must be determined
by the designer and are dependent on the characteris-
tics of the chosen crystal and board design.
C₁
X1
Crystal
C₁
C₂
Crystal
X2
C₂
Am186ED/EDLV
Note 1 ^{Microcontrollers}
a. Inverting Amplifier Configuration
Note 1: Use for Third Overtone Mode
XTAL Frequency L1 Value (Max)
20 MHz
12 µH ±20%
25 MHz
8.2 µH ±20%
33 MHz
4.7 µH ±20%
40 MHz
3.0 µH ±20%
200 pF
b. Crystal Configuration
Figure 8. Am186ED/EDLV Microcontrollers Oscillator Configurations
40
Am186ED/EDLV Microcontrollers