AM186ED Datasheet, PDF (41/88 Pages) Advanced Micro Devices – High Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers

PRELIMINARY
External Source Clock
Initialization and Processor Reset
Alternately, the internal oscillator can be driven from an Processor initialization or startup is accomplished by
external clock source. This source should be con- driving the RES input pin Low. RES must be held Low
nected to the input of the inverting amplifier (X1), with for 1 ms during power-up to ensure proper device ini-
the output (X2) not connected.
tialization. RES forces the Am186ED/EDLV microcon-
System Clocks
trollers to terminate all execution and local bus activity.
No instruction or bus activity occurs as long as RES is
The base system clock of AMD’s original 80C186 and active. After RES becomes inactive and an internal
80C188 microcontrollers is renamed CLKOUTA and processing interval elapses, the microcontroller begins
the additional output is called CLKOUTB. CLKOUTA execution with the instruction at physical location
and CLKOUTB operate at either the processor fre- FFFF0h, with UCS asserted with three wait states.
quency or the PLL frequency. The output drivers for RES also sets some registers to predefined values and
both clocks are individually programmable for disable. resets the watchdog timer.
Figure 9 shows the organization of the clocks.
Reset Configuration Register
The second clock output (CLKOUTB) allows one clock
to run at the PLL frequency and the other clock to run
at the power-save frequency. Individual drive enable
bits allow selective enabling of just one or both of these
clock outputs.
Power-Save Operation
The power-save mode of the Am186ED/EDLV micro-
controllers reduces power consumption and heat dissi-
T ^{pation, thereby extending battery life in portable}
systems. In power-save mode, operation of the CPU
and internal peripherals continues at a slower clock fre-
quency. When an interrupt occurs, the microcontroller
F ^{automatically returns to its normal operating frequency}
on the internal clock’s next rising edge of t₃.
Note: Power-save operation requires that clock-de-
pendent devices be reprogrammed for clock frequency
changes. Software drivers must be aware of clock fre-
A _{quency. The power-save divisor should not be set to}
operate the processor core below 100 kHz.
When the RES input is asserted Low, the contents of
the address/data bus (AD15–AD0) are written into the
reset configuration register. The system can place con-
figuration information on the address/data bus using
weak external pullup or pulldown resistors, or using an
external driver that is enabled during reset. The pro-
cessor does not drive the address/data bus during re-
set.
For example, the reset configuration register could be
used to provide the software with the position of a con-
figuration switch in the system. Using weak external
pullup and pulldown resistors on the address and data
bus, the system can provide the microcontroller with a
value corresponding to the position of the jumper dur-
ing a reset.
D ^{R X1,X2}
PLL
Mux
PSEN
Power-Save
Mux
Divisor
Processor Clock
/2
/1 to /128
CAF
CLKDIV2
CLKOUTA
Mux
CBF
CAD
Mux
Note: For frequencies under 16 MHz, use PLL bypass.
Figure 9. Clock Organization
Time
Delay
6 ns ±
CBD
CLKOUTB
Am186ED/EDLV Microcontrollers
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