AM186ED Datasheet, PDF (27/88 Pages) Advanced Micro Devices – High Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers

PRELIMINARY
covered by peripheral chip selects in the 80C186 and
80C188 microcontrollers. PCS0–PCS1 also have
extended wait state options.
PCS2/CTS1/ENRX1/PIO18
PCS3/RTS1/RTR1/PIO19
Peripheral Chip Select 3 (output, synchronous)
Ready-to-Send 1 (output, asynchronous)
Ready-to-Receive 1 (output, asynchronous)
Peripheral Chip Select 2 (output, synchronous)
PCS3—This pin provides the Peripheral Chip Select 3
Clear-to-Send 1 (input, asynchronous)
signal to the system when hardware flow control is not
Enable-Receiver-Request 1 (input, asynchronous)
enabled for asynchronous serial port 1. The PCS3
PCS2—This pin provides the Peripheral Chip Select 2
signal to the system when hardware flow control is not
enabled for asynchronous serial port 1. The PCS2
signal indicates to the system that a memory access is
in progress to the corresponding region of the
signal indicates to the system that a memory access is
in progress to the corresponding region of the
peripheral memory block (either I/O or memory
address space). The base address of the peripheral
memory block is programmable.
peripheral memory block (either I/O or memory The PCS chip selects can overlap either block of
address space). The base address of the peripheral DRAM. The PCS chip selects must have the same or
memory block is programmable.
greater number of wait states as the bank of DRAM
The PCS chip selects can overlap either block of
DRAM. The PCS chip selects must have the same or
greater number of wait states as the bank of DRAM
they overlap. The PCS signals take precedence over
DRAM accesses when DRAM and memory-mapped
peripherals overlap.
PCS2 is three-stated and held resistively High during a
T _{bus hold condition. In addition, PCS2 has a weak}
internal pullup resistor that is active during reset.
Unlike the UCS and LCS chip selects, the PCS outputs
F ^{assert with the multiplexed AD address bus. Note also}
that each peripheral chip select asserts over a 256-
byte address range, which is twice the address range
covered by peripheral chip selects in the 80C186 and
80C188 microcontrollers. PCS2 also has extended
A ^{wait state options.}
CTS1—This pin provides the Clear-to-Send signal for
asynchronous serial port 1 when the ENRX1 bit in the
AUXCON register is 0 and hardware flow control is
enabled for the port (FC bit in the serial port 1 control
R register is set). The CTS1 signal gates the
transmission of data from the associated serial port
transmit register. When CTS1 is asserted, the
transmitter begins transmission of a frame of data, if
D ^{any is available. If CTS1 is deasserted, the transmitter}
they overlap. The PCS signals take precedence over
DRAM accesses when DRAM and memory-mapped
peripherals overlap.
PCS3 is three-stated and held resistively High during a
bus hold condition. In addition, PCS3 has a weak
internal pullup resistor that is active during reset.
Unlike the UCS and LCS chip selects, the PCS outputs
assert with the multiplexed AD address bus. Note also
that each peripheral chip select asserts over a 256-
byte address range, which is twice the address range
covered by peripheral chip selects in the 80C186 and
80C188 microcontrollers. PCS3 also has extended
wait state options.
RTS1—This pin provides the Ready-to-Send signal for
asynchronous serial port 1 when the RTS1 bit in the
AUXCON register is 1 and hardware flow control is
enabled for the port (FC bit in the serial port 1 control
register is set). The RTS1 signal is asserted when the
associated serial port transmit register contains data
which has not been transmitted.
RTR1—This pin provides the Ready-to-Receive signal
for asynchronous serial port 1 when the RTS1 bit in the
AUXCON register is 0 and hardware flow control is
enabled for the port (FC bit in the serial port 1 control
register is set). The RTR1 signal is asserted when the
holds the data in the serial port transmit register. The associated serial port receive register does not contain
value of CTS1 is checked only at the beginning of the valid, unread data.
transmission of the frame.
PCS5/A1/PIO3
ENRX1—This pin provides the Enable Receiver
Request for asynchronous serial port 1 when the
ENRX1 bit in the AUXCON register is 1 and hardware
Peripheral Chip Select 5 (output, synchronous)
Latched Address Bit 1 (output, synchronous)
flow control is enabled for the port (FC bit in the serial
PCS5—This pin indicates to the system that a memory
port 1 control register is set). The ENRX1 signal
access is in progress to the sixth region of the
enables the receiver for the associated serial port.
peripheral memory block (either I/O or memory
address space). The base address of the peripheral
memory block is programmable.
The PCS chip selects can overlap either block of
DRAM. The PCS chip selects must have the same or
greater number of wait states as the bank of DRAM
Am186ED/EDLV Microcontrollers
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