AM186ED Datasheet, PDF (64/88 Pages) Advanced Micro Devices – High Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers

PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges
Read Cycle (20 MHz and 25 MHz)
Preliminary
Parameter
20 MHz
25 MHz
No. Symbol
Description
Min
Max
Min
Max Unit
General Timing Requirements
1
t_DVCL Data in Setup
2
t_CLDX
Data in Hold^(c)
General Timing Responses
10
10
ns
3
3
ns
3
t_CHSV Status Active Delay
0
4
t_CLSH Status Inactive Delay
0
5
t_CLAV AD Address Valid Delay and BHE
0
6
t_CLAX Address Hold
0
8
t_CHDX Status Hold Time
0
9
t_CHLH ALE Active Delay
10
t_LHLL ALE Width
t_CLCL – 10 = 40
11
t_CHLL ALE Inactive Delay
12
t_AVLL
AD Address Valid to ALE Low^(a)
t_CLCH –2
13
t_LLAX AD Address Hold from ALE Inactive^(a)
t_CHCL –2
14
t_AVCH AD Address Valid to Clock High
0
15
t_CLAZ AD Address Float Delay
t_CLAX =0
16
t_CLCSV MCS/PCS Active Delay
0
17
t_CXCSX MCS/PCS Hold from Command Inactive^(a)
18
t_CHCSX MCS/PCS Inactive Delay
19
t_DXDL DEN Inactive to DT/R Low^(a)
20
t_CVCTV Control Active Delay 1^(b)
21
t_CVDEX DEN Inactive Delay
22
t_CHCTV Control Active Delay 2^(b)
A ₂₃
t_LHAV ALE High to Address Valid
99
t_PLAL PCS Active to ALE Inactive
Read Cycle Timing Responses
24
t_AZRL AD Address Float to RD Active
R 25
t_CLRL RD Active Delay
26
t_RLRH RD Pulse Width
27
t_CLRH RD Inactive Delay
D²⁸
t_RHLH RD Inactive to ALE High^(a)
t_CLCH – 2
0
0
0
0
0
20
15
0
0
2t_CLCL – 15 = 85
0
t_CLCH – 3
29
t_RHAV RD Inactive to AD Address Active^(a)
t_CLCL – 10 = 40
41
t_DSHLH DS Inactive to ALE Active
t_CLCH – 2=21
59
t_RHDX RD High to Data Hold on AD Bus^(c)
0
66
t_AVRL A Address Valid to RD Low^(a)
t_CLCL+ t_CHCL–3
67
t_CHCSV CLKOUTA High to LCS/UCS Valid
0
68
t_CHAV CLKOUTA High to A Address Valid
0
25
0
20
ns
25
0
20
ns
25
0
20
ns
25
0
20
ns
0
ns
F ^{T 25}
20
t_CLCL – 10 =30
25
20
t_CLCH – 2
t_CHCL – 2
0
25
t_CLAX = 0
20
25
0
20
t_CLCH – 2
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
0
20
ns
0
ns
25
0
20
ns
25
0
20
ns
25
0
20
ns
15
ns
28
15
24
ns
0
ns
25
0
20
ns
2t_CLCL – 15 = 65
ns
25
0
20
ns
t_CLCH – 3
ns
t_CLCL – 10 = 30
ns
t_CLCH – 2=16
ns
0
ns
t_CLCL + t_CHCL–3
ns
25
0
20
ns
25
0
20
ns
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions
are with C_L =50 pF. For switching tests, V_IL=0.45 V and V_IH =2.4 V, except at X1 where V_IH =V_CC – 0.5 V.
a Equal loading on referenced pins.
b This parameter applies to the DEN, DS, INTA1–INTA0, WR, WHB, and WLB signals.
c If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly.
64
Am186ED/EDLV Microcontrollers