AM186ED Datasheet, PDF (68/88 Pages) Advanced Micro Devices – High Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers

PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges
Write Cycle (33 MHz and 40 MHz)
Preliminary
Parameter
33 MHz
40 MHz
No. Symbol
Description
Min
Max
Min
Max Unit
General Timing Responses
3
t_CHSV Status Active Delay
0
4
t_CLSH Status Inactive Delay
0
5
t_CLAV AD Address Valid Delay and BHE
0
6
t_CLAX Address Hold
0
7
t_CLDV Data Valid Delay
0
8
t_CHDX Status Hold Time
0
9
t_CHLH ALE Active Delay
10
t_LHLL ALE Width
t_CLCL – 10 = 20
11
t_CHLL ALE Inactive Delay
12
t_AVLL AD Address Valid to ALE Low^(a)
13
t_LLAX AD Address Hold from ALE Inactive^(a)
t_CLCH – 2
t_CHCL– 2
14
t_AVCH AD Address Valid to Clock High
0
16
t_CLCSV MCS/PCS Active Delay
17
t_CXCSX MCS/PCS Hold from Command Inactive^(a)
0
t_CLCH – 2
18
t_CHCSX MCS/PCS Inactive Delay
19
t_DXDL DEN Inactive to DT/R Low^(a)
20
t_CVCTV Control Active Delay 1^(b)
21
t_CVDEX DS Inactive Delay
22
t_CHCTV Control Active Delay 2
23
t_LHAV ALE High to Address Valid
99
t_PLAL PCS Active to ALE Inactive
Write Cycle Timing Responses
30
t_CLDOX Data Hold Time
31
t_CVCTX Control Inactive Delay^(b)
32
t_WLWH WR Pulse Width
33
t_WHLH WR Inactive to ALE High^(a)
R 34
t_WHDX Data Hold after WR^(a)
35
t_WHDEX WR Inactive to DEN Inactive^(a)
41
t_DSHLH DS Inactive to ALE Active
D⁶⁵
t_AVWL A Address Valid to WR Low
67
t_CHCSV CLKOUTA High to LCS/UCS Valid
0
0
A0
0
0
10
12
0
0
2t_CLCL – 10= 50
t_CLCH – 2
t_CLCL – 10 = 20
t_CLCH – 3
t_CLCH – 2=11.5
t_CLCL + t_CHCL – 3
0
68
t_CHAV CLKOUTA High to A Address Valid
0
87
t_AVBL A Address Valid to WHB, WLB Low
t_CHCL – 3
98 t_DSHDIW DS High to Data Invalid—Write
20
15
0
12 ns
15
0
12 ns
15
0
12 ns
0
ns
15
0
12 ns
0
ns
15
12 ns
t_CLCL – 5= 20
ns
F ^{T 15}
12
t_CLCH – 2
t_CHCL– 2
0
15
0
12
t_CLCH – 2
15
0
12
0
15
0
12
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
0
12 ns
15
0
12 ns
7.5
ns
20
10
18 ns
0
ns
15
0
12 ns
2t_CLCL – 10 = 40
ns
t_CLCH – 2
ns
t_CLCL – 10 = 15
ns
t_CLCH –3
ns
t_CLCH – 2=9.25
ns
t_CLCL+t_CHCL–1.25
ns
15
0
10 ns
15
0
10 ns
15
t_CHCL – 1.25
12 ns
15
ns
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions
are with C_L =50 pF. For switching tests, V_IL=0.45 V and V_IH =2.4 V, except at X1 where V_IH =V_CC – 0.5 V.
a Testing is performed with equal loading on referenced pins.
b This parameter applies to the DEN, DS, INTA1–INTA0, WR, WHB, and WLB signals.
68
Am186ED/EDLV Microcontrollers