AM186ED Datasheet, PDF (21/88 Pages) Advanced Micro Devices – High Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers

PRELIMINARY
PIN DESCRIPTIONS
Pins That Are Used by Emulators
The following pins are used by emulators: A19–A0,
system during the remaining periods of that cycle (t₂,
t₃, and t₄).
AD7–AD0, ALE, BHE/ADEN, CLKOUTA, RD, S2–S0, The address phase of these pins can be disabled. See
S6/CLKDIV2, and UZI.
the ADEN description with the BHE/ADEN pin. When
Many emulators require S6/CLKDIV2 and UZI to be
configured in their normal functionality as S6 and UZI,
WHB is deasserted, these pins are three-stated during
t₂, t₃, and t_4.
not as PIOs. If BHE/ADEN is held Low during the rising During a bus hold or reset condition, the address and
edge of RES, S6 and UZI are configured in their normal data bus is in a high-impedance state.
functionality.
During a power-on reset, the address and data bus
Pin Terminology
The following terms are used to describe the pins:
pins (AD15–AD0) can also be used to load system
configuration information into the internal reset
configuration register.
Input—An input-only pin.
When accesses are made to 8-bit-wide memory
Output—An output-only pin.
regions, AD15–AD8 drive their corresponding address
Input/Output—A pin that can be either input or output
(I/O).
Synchronous—Synchronous inputs must meet setup
and hold times in relation to CLKOUTA. Synchronous
outputs are synchronous to CLKOUTA.
T ^{Asy nchronous—In puts o r o utp uts th at a re}
asynchronous to CLKOUTA.
A19–A0
(A19/PIO9, A18/PIO8, A17/PIO7)
F _{Address Bus (output, three-state, synchronous)}
These pins supply nonmultiplexed memory or I/O
addresses to the system one half of a CLKOUTA period
earlier than the multiplexed address and data bus
A _{(AD15–AD0). During a bus hold or reset condition, the}
address bus is in a high-impedance state.
While the Am186ED/EDLV microcontrollers are directly
connected to DRAM, A19–A0 will serve as the
R ^{nonmultiplexed address bus for SRAM, FLASH,}
PROM, EPROM, and peripherals. The odd address
pins (A17, A15, A13, A11, A9, A7, A5, A3, and A1) will
have both the row and column address during a DRAM
D ^{space access. The odd address signals connect}
signals throughout the access. If the disable address
phase and 8-bit mode are selected (see the ADEN
description with the BHE/ADEN pin), then AD15–AD8
are three-stated during t₁ and driven with their
corresponding address signal from t₂ to t₄.
AD7–AD0
Address and Data Bus (input/output, three-state,
synchronous, level-sensitive)
These time-multiplexed pins supply partial memory or
I/O addresses, as well as data, to the system. This bus
supplies the low-order 8 bits of an address to the
system during the first period of a bus cycle (t₁), and it
supplies data to the system during the remaining
periods of that cycle (t₂, t₃, and t₄). In 8-bit mode, AD7–
AD0 supplies the data for both high and low bytes.
The address phase of these pins can be disabled. See
the ADEN pin description with the BHE/ADEN pin.
When WLB is deasserted, these pins are three-stated
during t₂, t₃, and t_4.
During a bus hold or reset condition, the address and
data bus is in a high-impedance state.
During a power-on reset, the address and data bus
pins (AD15–AD0) can also be used to load system
directly to the row and column multiplexed address bus
configuration information into the internal reset
of the DRAM. The even address pins (A18, A16, A14,
configuration register.
A12, A10, A8, A6, A4, A2, and A0) and A19 will have
the initial address asserted during the full DRAM ALE
access. These signals will not transition during a
DRAM access.
AD15–AD8
Address Latch Enable (output, synchronous)
This pin indicates to the system that an address ap-
pears on the address and data bus (AD15–AD0). The
Address and Data Bus (input/output, three-state,
synchronous, level-sensitive)
address is guaranteed to be valid on the trailing edge
of ALE. This pin is three-stated during ONCE mode.
AD15–AD8—These time-multiplexed pins supply
memory or I/O addresses and data to the system. This
bus can supply an address to the system during the
first period of a bus cycle (t₁). It supplies data to the
ALE is three-stated and held resistively Low during a
bus hold condition. In addition, ALE has a weak internal
pulldown resistor that is active during reset, so that an
external device does not get a spurious ALE during
reset.
Am186ED/EDLV Microcontrollers
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