AM186ED Datasheet, PDF (45/88 Pages) Advanced Micro Devices – High Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers

PRELIMINARY
TIMER CONTROL UNIT
after reset. It can only be modified a single time by a
There are three 16-bit programmable timers and a
watchdog timer on the Am186ED/EDLV microcontrol-
lers.
keyed sequence of writes to the watchdog timer control
register (WDTCON) following reset. This single write
can either disable the timer or modify the timeout pe-
riod and the action taken upon timeout. A keyed se-
Timer 0 and timer 1 are connected to four external pins quence is also required to reset the current WDT count.
(each one has an input and an output). These two tim- This behavior ensures that randomly executing code
ers can be used to count or time external events, or to will not prevent a WDT event from occurring.
generate nonrepetitive or variable-duty-cycle wave-
forms. When pulse width demodulation is enabled,
timer 0 and timer 1 are used to measure the width of
the High and Low pulses on the PWD pin. (See the
The WDT supports up to a 1.67-second timeout period
in a 40-MHz system. After reset, the WDT is enabled
and the timeout period is set to its maximum value.
Pulse Width Demodulation section on page 45.)
The WDT can be configured to cause either an NMI in-
Timer 2 is not connected to any external pins. It can be
used for real-time coding and time-delay applications.
It can also be used as a prescaler to timers 0 and 1 or
to synchronize DMA transfers.
terrupt or a system reset upon timeout. If the WDT is
configured for NMI, the NMIFLAG in the WDTCON reg-
ister is set when the NMI is generated. The NMI inter-
rupt service routine (ISR) should examine this flag to
determine if the interrupt was generated by the WDT or
The programmable timers are controlled by eleven 16-
bit registers in the peripheral control block. A timer’s
timer-count register contains the current value of that
timer. The timer-count register can be read or written
with a value at any time, whether the timer is running or
not. The microcontroller increments the value of the
T ^{timer-count register each time a timer event occurs.}
Each timer also has a maximum-count register that de-
fines the maximum value the timer can reach. When
the timer reaches the maximum value, it resets to 0
F _{during the same clock cycle. The value in the maxi-}
mum-count register is never stored in the timer-count
register. Also, timers 0 and 1 have a secondary maxi-
mum-count register. Using both the primary and sec-
ondary maximum-count registers lets the timer
A _{alternate between two maximum values.}
If the timer is programmed to use only the primary max-
imum-count register, the timer output pin switches Low
for one clock cycle after the maximum value is
R ^{reached. If the timer is programmed to use both of its}
maximum-count registers, the output pin indicates
which maximum-count register is currently in control,
thereby creating a waveform. The duty cycle of the
D ^{waveform depends on the values in the maximum-}
by an external source. If the NMIFLAG is set, the ISR
should clear the flag by writing the correct keyed se-
quence to the WDTCON register. If the NMIFLAG is set
when a second WDT timeout occurs, a WDT system
reset is generated rather than a second NMI event.
When the processor takes a WDT reset, either due to
a single WDT event with the WDT configured to gener-
ate resets or due to a WDT event with the NMIFLAG
set, the RSTFLAG in the WDTCON register is set. This
allows system initialization code to differentiate be-
tween a hardware reset and a WDT reset and take ap-
propriate action. The RSTFLAG is cleared when the
WDTCON register is read or written. The processor
does not resample external pins during a WDT reset.
This means that the clocking, the reset configuration
register, and any other features that are user-select-
able during reset do not change when a WDT system
reset occurs. All other activities are identical to those of
a normal system reset.
Note: The Watchdog Timer (WDT) is active after re-
set.
PULSE WIDTH DEMODULATION
For many applications, such as bar-code reading, it is
count registers.
necessary to measure the width of a signal in both its
Each timer is serviced every fourth clock cycle, so a
timer can operate at a speed of up to one-quarter of the
internal clock frequency. A timer can be clocked exter-
nally at this same frequency; however, because of in-
ternal synchronization and pipelining of the timer
High and Low phases. The Am186ED/EDLV microcon-
trollers provide a pulse-width demodulation (PWD) op-
tion to fulfill this need. The PWD bit in the System
Configuration Register (SYSCON) enables the PWD
option. Analog-to-digital conversion is not supported.
circuitry, the timer output can take up to six clock cycles
In PWD mode, TMRIN0, TMRIN1, INT2, and INT4 are
to respond to the clock or gate input.
configured internal to the microcontroller to support the
Watchdog Timer
detection of rising and falling edges on the PWD input
pin (INT2/INTA0/PWD) and to enable either timer 0
The Am186ED/EDLV microcontrollers provide a true
when the signal is High or timer 1 when the signal is
watchdog timer function. The Watchdog Timer (WDT)
Low. The INT4, TMRIN0, and TMRIN1 pins are not
can be used to regain control of the system when soft-
used in PWD mode and so are available for use as
ware fails to respond as expected. The WDT is active
PIOs.
Am186ED/EDLV Microcontrollers
45