AM186ED Datasheet, PDF (37/88 Pages) Advanced Micro Devices – High Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers

PRELIMINARY
Table 6. DRAM Pin Interface
Byte-Write Enables
AM186ED/EDLV
Microcontroller Pins
A1
MA0
DRAM Pin
The Am186ED/EDLV microcontrollers provide the
WHB (Write High Byte) and WLB (Write Low Byte) sig-
nals, which act as byte-write enables.
A3
MA1
A5
MA2
A7
MA3
A9
MA4
A11
MA5
A13
MA6
WHB is the logical OR of BHE and WR. WHB is Low
when BHE and WR are both Low. WLB is the logical
OR of A0 and WR. WLB is Low when A0 and WR are
both Low.
The byte-write enables are driven in conjunction with
the nonmultiplexed address bus as required for the
write timing requirements of common SRAMs.
A15
A17
RAS0
MA7
MA8
RAS (Bank 0)
Data Strobe Bus Interface Option
The Am186ED/EDLV microcontrollers provide an
asynchronous bus interface that allows the use of 68K-
RAS1
RAS (Bank 1)
type peripherals. This implementation combines a DS
UCAS
LCAS
RD
WR
UCAS (AD15–AD8 Byte)
LCAS (AD7–AD0 Byte)
OE
WE
T _{Programmable Bus Sizing}
The Am186ED/EDLV microcontrollers allow program-
mability for data bus widths through fields in the Auxil-
F ^{iary Configuration Register (AUXCON) , as shown in}
Table 7. The USIZ bit in AUXCON is only configurable
if the boot mode is 8-bit at reset.
The width of the data access should not be modified
while the processor is fetching instructions from the as-
A _{sociated address space.}
Table 7. Programming the Bus Width of
Am186ED/EDLV Microcontrollers
R _Space
D^UCS
AUXCON
Field Value
USIZ
0
Bus
Width
16 bits
Comments
Dependent
on boot
option¹
data strobe signal (multiplexed with DEN) with an asyn-
chronous ARDY ready input. When DS is asserted, the
data and address signals are valid.
A chip select signal, ARDY, DS, and other control sig-
nals (RD/WR) can control the interface of 68K-type ex-
ternal peripherals to the AD bus.
DRAM INTERFACE
The Am186ED/EDLV microcontrollers support up to
two banks of DRAM. The use of DRAM can signifi-
cantly reduce the memory costs for applications using
more than 64K of RAM. No performance is lost except
for the slight overhead of periodically refreshing the
DRAM. The lower bank of DRAM uses the LCS space.
The upper bank of DRAM uses the UCS space. Either,
neither, or both banks can be activated. When either
bank is activated, the UCAS and LCAS are enabled,
and the DRAM address multiplexing is enabled on the
A19–A0 bus. When DRAM is activated, the corre-
sponding memory bus size should be set to 16-bit. The
use of 8-bit-wide DRAM is not supported. All refreshes
to DRAM are 7 clocks long. The refreshes must be sep-
arately enabled in the RCU.
The improved memory timing specifications of the
Am186ED/EDLV microcontrollers allow for zero-wait-
1
8 bits
state operation using 50-ns DRAM at a 40-MHz clock
LCS
LSIZ
I/O
IOSIZ
0
16 bits Default
1
8 bits
0
16 bits Default
speed. 60-ns DRAM requires one wait state at 40 MHz
and zero wait states at 33 MHz and below. 70-ns
DRAM requires two wait states at 40 MHz, one wait
state at 33 MHz, and zero wait states at 25 MHz and
1
8 bits
below. This reduces overall system cost by enabling
Other
MSIZ
0
16 bits Default
the use of commonly available memory speeds and
1
8 bits
taking advantage of DRAM’s lower cost per bit over
SRAM.
Note:
1. UCS width on reset is determined by the S2/BTSEL
pin. If UCS boots as a 16-bit space, it is not re-con-
figurable to 8-bit.
Am186ED/EDLV Microcontrollers
37