EPXA4 Datasheet, PDF (8/34 Pages) Altera Corporation – Excalibur Devices

Errata Sheet - Appendix A
A.1
A.1.1
A.1.2
Errata for the ARM920T AHB Wrapper Module
This section documents errata in the ARM920T AHB wrapper module,
which is used in the Excalibur device.
Linefill Counter—Category 2
The burst counter for a cache linefill is incorrectly pre-loaded if the linefill
follows a waited access. This results in 9 reads being performed on the
AHB bus rather than the required 8. The ARM920T receives the correct
data: the only effects of the extra read are that an extra cycle is taken up on
the bus, and any side-effects are due to the addressed area being read-
sensitive (e.g. a FIFO).
Work Around
The software workaround is to ensure that only address areas which are
not read-sensitive are cached.
Error Response—Category 2
There is a bug in the ERROR response functionality in the wrapper. An
ERROR response should only be accepted by the ARM920T if it is in
response to a non-cacheable or non-bufferable access. The AHB wrapper
only adds wait states to non-bufferable writes when ERROR support is
added, since buffered writes do not need to be held up in order to
propagate the respons. However, the ERROR response from the AHB is
still propagated to the ASB in all cases. Thus a C/B access to the AHB
which results in an ERROR response, followed by a NC/NB* access,
means that the ERROR response appears on the ARM920T ASB interface
as the response to the NC/NB access and so is accepted.
Work Around
The software workaround is to never access address regions which are
capable of generating error responses with C/B accesses.
*NC Non-cacheable
NB Non-bufferable
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