EPXA4 Datasheet, PDF (3/34 Pages) Altera Corporation – Excalibur Devices

Excalibur EPXA4 Devices Errata Sheet
2.2 Locking Mechanism is Non-Functional
Using the DPRAM locking mechanism for simultaneous accesses from the
stripe and PLD results in incorrect memory accesses. Simultaneous
accesses to different addresses are not affected.
AHB Bridges
3.1
Work Around
Do not use the DPRAM locking feature. Instead, use a handshake
mechanism such as a semaphore to control PLD and stripe accesses to
common DPRAM addresses.
This section provides further information about errata in the AHB
bridges.
Back-to-back Transactions through the PLD-to-Stripe Bridge Can
Cause Lock-up
If the non-sequential address phase of a new transaction occurs in the
same clock cycle as the final data phase of the previous transaction, the
slave interface of the PLD-to-stripe bridge issues erroneous wait states
causing masters to the PLD-to-stripe bridge in the PLD to lock up.
Incorrect transactions can occur on AHB2.
Work Around
Insert an IDLE address phase between all transactions.
3.2 Corrupted State of the Stripe-to-PLD Bridge after PLD
Reconfiguration under Processor Control
If the MASTER_HCLK signal is active during PLD reconfiguration under
processor control, the stripe-to-PLD bridge can become corrupted before
the device enters user mode. The bridge cannot respond to AHB2
transactions, which causes the AHB2 bus to lock up. Gating the source of
MASTER_HCLK with INIT_DONE does not prevent the potential lock up.
Work Arounds
To avoid corrupting the bridge during PLD reconfiguration, the clock
driving MASTER_HCLK must be inactive before the PLD enters user mode.
This can be achieved in either of the following ways:
■ Software work around—compile the design using Quartus^® II version
2.1 or higher. These versions of Quartus II route the stripe-to-PLD
bridge signals specifically to avoid the bridge lock up. The routing
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