EPXA4 Datasheet, PDF (22/34 Pages) Altera Corporation – Excalibur Devices

Errata Sheet - Appendix A
It is occasionally useful to be able to determine the exact cycles on which
instructions are executed, for example to perform basic performance
analysis or to diagnose problems with the memory system. The
information can be preserved by one of two methods:
■ By selecting cycle-accurate mode, the ETM can be configured to cause
trace to be captured on every cycle during a trace region.
■ By using a trace port analyzer or logic analyzer which is capable of
saving timestamps with each cycle of trace.
Under some circumstances, extra instruction execution cycles are
reported alongside a previous instruction, making it appear that that
instruction took longer to execute instead. While the number of cycles that
a sequence of instructions takes to execute is correctly reported, the
number of cycles taken by individual instructions is not.
This erratum does not affect ETM9 Rev 0a, although ARM strongly
recommends that the latest revision of ETM9 is used in all new designs.
The erratum was introduced as a result of improvements to the
effectiveness of the FIFOFULL mechanism, although it is occurs whether
FIFOFULL is enabled or not.
Table 6 shows an example where a stall caused by an LDR is traced with
the wrong instruction. Note that the ETM reports an instruction when the
following instruction begins execution. Therefore the time taken by an
instruction is the time between that instruction and the previous
instruction in the trace.
Table 6. Example of correct and incorrect trace in the presence of stalls (Part 1 of 2)
Cycle
500
501
502
503
504
505
506
507
508
509
510
Address Instruction
1000
1004
1008
100C
1010
1014
1018
101C
1020
1024
NOP
NOP
NOP
NOP
NOP
NOP
NOP
LDR
(LDR stalled)
NOP
B 1040
Actual trace
Expected
trace
IE (instruction
IE for 1000
executed) for 1000
Notes
Instruction enters ETM pipeline
1004 triggers tracing of 1000, 9 cycles later
Most of ETM pipeline stalled along with processor
pipeline
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