EPXA4 Datasheet, PDF (23/34 Pages) Altera Corporation – Excalibur Devices

Errata Sheet - Appendix A
Table 6. Example of correct and incorrect trace in the presence of stalls (Part 2 of 2)
511
(Branch delay) WT (wait)
512
(Branch delay) IE for 1004
513
1040
NOP
IE for 1008
514
IE for 100C
515
IE for 1010
516
IE for 1014
517
IE for 1018
518
IE for 101C
519
IE for 1020
520
WT
521
WT
522
IE for 1024
IE for 1004
IE for 1008
IE for 100C
IE for 1010
IE for 1014
IE for 1018
WT
IE for 101C
IE for 1020
WT
WT
IE for 1024
Stall in ETM pipeline observed after only 3 cycles
Stall should be observed in line with other
instructions
Stalls caused by the processor are correctly
reported
Instruction traced upon completion
Conditions
As shown in Table 6, only external stalls that are caused by deasserting
CLKEN (such as memory stalls) are misreported. All stalls caused by the
processor, including branch delays, register interlocks and coprocessor
busy-waits, are reported correctly. External (CLKEN) stalls are reported 6
cycles early.
Implications
It is hard to use the timestamp information to gain information on stalls
caused by the memory system. While this is beyond the scope of the
original design aims of the ETM, precise stall information has proven to
be extremely useful to some users in debugging system level issues.
Workaround
It is often possible to model the behavior of the core as it would behave if
there were no external stalls to determine which stalls are external and
which are internal. To do this in all situations would require a complete
cycle-accurate model of the core. However, in most cases the number of
cycles required by each instruction can be easily predicted, and is
documented in the Technical Reference Manual for the core.
Altera Corporation
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