EPXA4 Datasheet, PDF (25/34 Pages) Altera Corporation – Excalibur Devices

Errata Sheet - Appendix A
Table 7. Example of how to calculate the correct location of a stall (Part 2 of 2)
618
IE for 2018
WT
The stall is far more likely to
correspond to 201C, as this causes a
LDR to on-chip memory. We can
therefore deduce that this LDR
caused precisely 1 stall cycle.
619
IE for 201C
IE for 201C
620
IE for 2020
IE for 2020
The stall could not correspond to this
load, as it is not 6 cycles ahead of a
detected external stall in the trace.
621
IE for 2024
IE for 2024
Note that the total number of cycles
taken for the sequence of instructions
is reported correctly.
Note: If 2018 is also an LDR, rather than an ADD, then it would not be
possible to determine which of the two instructions 2018 or 201C caused
the stall.
A.2.7
FIFOFULL LOW for one cycle during overflow—Category 3
Description
Although FIFOFULL correctly becomes asserted when the space available
in the FIFO is less than the minimum value specified in the FIFOFULL
Level register of the ETM (register 0x0b), it incorrectly becomes de-
asserted for a single cycle when the FIFO overflows.
Conditions
This occurs for one cycle, on the same cycle in which the FIFO overflows.
Implications
One extra cycle of trace can be lost during FIFO overflow. Since this case
only occurs when overflow is already about to occur, the ability of
FIFOFULL to prevent overflow is unaffected.
Workaround
None required. The erratum causes the loss of an extra cycle of trace when
there is an overflow, so the effect is not significant.
Implications of workaround
No implications.
Altera Corporation
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