EPXA4 Datasheet, PDF (11/34 Pages) Altera Corporation – Excalibur Devices

Errata Sheet - Appendix A
Conditions
Extended wait-state periods can be caused by cache misses in cached
systems, or the use of a slow memory system. Consequently, the problem
is unlikely to occur in uncached systems or in systems where the speed of
the memory is close to that of the processor. Since the clock speed on the
ARM920T and ARM922T processors is slowed to that of the memory
when a cache miss occurs, memory speed is not an issue on these
processors, and consequently this erratum is less likely to occur on
systems with these devices.
The block data transfer instruction must be executing when the overflow
occurs. The instructions which fall into this category are as follows:
■ ARM instructions:
LDM, STM, SWP, SWPB, LDC, STC, LDRD, STRD, MCRR, MRRC.
■ Thumb instructions:
POP, PUSH, LDMIA, STMIA.
The wait-state period must begin before the overflow occurs. It is possible
for an overflow to occur after the wait-state has begun due to trace
continuing to enter the FIFO from the ETM pipeline. The wait-state period
must continue until after the ETM has recovered from the overflow,
having drained its FIFO of all pending trace.
The problem is more likely to occur with a small FIFO than a large FIFO
for two reasons:
■ A smaller FIFO is more likely to overflow.
■ Once an overflow has occurred, a smaller FIFO takes less time to
drain. Consequently, the length of the extended wait-state period
required for the problem to occur is reduced.
As a result, the problem is most likely to occur with the small ETM
configuration, and least likely with the large ETM configuration.
The minimum number of cycles required to drain the FIFO, and therefore
the theoretical minimum length of the wait-state period, is shown in
Table 3 on page 12.
Altera Corporation
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