EPXA4 Datasheet, PDF (19/34 Pages) Altera Corporation – Excalibur Devices

A.2.3
Errata Sheet - Appendix A
Instruction displayed before and after overflow—Category 2
Description
When the FIFO overflows, the last instruction to be traced immediately
before overflow may be repeated on recovery from overflow.
Conditions
The instruction must be executing when the overflow occurs and remain
so until trace is re-enabled following overflow. This generally only arises
if a large number of wait states occur. Consequently it should only occur
in cached systems during a cache miss, or when using a very slow
memory system.
Since the ETM FIFOFULL signal attempts to preemptively insert
processor wait states to prevent the FIFO from overflowing, having
FIFOFULL enabled can also increase the occurrence of this problem.
Implications
It can appear that an instruction is executed twice when it was only
executed once.
Workaround for tools vendors
The development tools should be modified to discard the instruction
before the overflow, only displaying the instruction after overflow when
the addresses of the instructions before and after overflow match.
Occasionally this would cause an instruction to be discarded
unnecessarily, but a much larger number of instructions would already
have been discarded due to the overflow.
It is important that the instruction before overflow is the one to be
discarded, and not the one following overflow recovery, in case the
erratum is falsely detected. If trace is turned off during overflow
(TraceEnable goes LOW), then enabled again (TraceEnable goes HIGH)
some time after overflow recovery, the first instruction to be traced
following overflow may be significant and must be traced.
Implications of workaround
An extra instruction will occasionally be lost during an overflow
occurring in a loop. This will not be detectable by the user.
Altera Corporation
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