EPXA4 Datasheet, PDF (33/34 Pages) Altera Corporation – Excalibur Devices

A.3.5
Errata Sheet - Appendix A
Register controlled shift data operations where the destination is
the PC (ARM9TDMI–1)—Category 3
ARM9 Bug tracking database entry : CPC00_CAM_000001
Summary
A data operation with a register controlled shift to the PC may calculate
an incorrect result
Description
This fault is exhibited by any data operation involving a register-specified
shift with the Program Counter as the destination. This is in effect a
calculated branch, with an unusual branch address calculation. The
branch target address calculated by the instruction is incorrect.
The ARM C compiler will not generate this instruction. Other compilers
are extremely unlikely to produce this instruction, as no standard high
level languages source code constructs which would map to this
instruction.
It is also extremely unlikely that this instruction has been used in
assembler code, as is explained below.
Conditions
Exists for any instruction that involves a register-specified shift or rotate
operation with the PC as the destination for the resulting data. The fault
does not occur for an immediate specified shift or rotate to the PC.
Implications
Data operations involving a register controlled shift and where the
destination register is the PC have an unpredictable behaviour on an
ARM9TDMI processor core and any processor containing an
ARM9TDMI; for example ARM920T.
The current ARM compiler cannot generate instructions of this class and
so this would only be encountered in hand coded assembler. ARM’s
software staff have considered possible uses for such an instruction in
assembler code, and have only found one theoretical use for this
instruction, which is a strange branch table described below.
For these reasons this erratum is not expected to cause any restrictions or
problems in using the ARM9TDMI.
Altera Corporation
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