EPXA4 Datasheet, PDF (4/34 Pages) Altera Corporation – Excalibur Devices

Excalibur EPXA4 Devices Errata Sheet
utilizes three extra logic elements in the device and adds minimal
corresponding delay to the bridge timing. If logic element usage or
bridge timing is critical to your design, you can disable the automatic
Quartus II routing option by adding the following parameter to the
defparam section of the stripe instantiation file generated by the
MegaWizard^®:
lpm_instance.xa_configuration_fix = “FALSE“
If this routing option is disabled, you must use the hardware work
around described below to ensure correct functionality.
1
If you use this recommended software workaround, ensure
that the Remove Redundant Logic Cells option is not
selected for your project.
1
If the Perform WYSIWYG Primitive Resynthesis option is
selected for your project, you may receive warnings that the
stripe signals were not routed correctly. To eliminate the
warnings, re-run the MegaWizard in Quartus II version 2.2.
This creates an additional settings file (alt_exc_stripe.esf) to
ensure that the required logic elements are implemented.
■ Hardware work around—ensure that the external clock that drives
MASTER_HCLK is inactive before the PLD is put into reconfiguration
mode, and is enabled again only after the PLD enters user mode.
INIT_DONE can be used only to activate the external clock. It should
not be used to disable the clock, for the following reason: when
reconfiguration begins, INIT_DONE does not drop to low in time to
prevent the error. You must use another method to disable the
external clock, such as using an external device to control the clock
input.
If a PLL in the PLD portion of the device is used to drive
MASTER_HCLK, you must drive the PLL CLKLK_ENA signal with
INIT_DONE so that the PLL output does not drive MASTER_HCLK
before the device is in user mode. See AN 115: Using the ClockLock &
ClockBoost PLL Features in APEX Devices for information on enabling
the PLD PLLs with INIT_DONE.
4
Altera Corporation