EPXA4 Datasheet, PDF (13/34 Pages) Altera Corporation – Excalibur Devices

Errata Sheet - Appendix A
Implications
While instruction trace remains unaffected, the user is unable to ascertain
whether the data trace is correct.
The erratum must be considered when the following occur together:
■ An overflow is reported.
■ The first instruction traced following the overflow is a block data
transfer instruction.
■ The first instruction traced following the overflow includes data
trace.
■ Either:
– The address of the instruction traced both before and after
overflow is the same
– The address of the instruction traced after overflow is the next
instruction address that would have been expected had the
overflow not occurred.
Examples of this case are:
– The instructions before and after overflow are both LDMIA
instructions at address 1000.
– The instruction before overflow is a branch at address 1010 that
failed its condition codes, and the instruction after overflow is an
STMDB at address 1014.
– The instruction before overflow is an LDR to the pc at address
1020 which caused a branch to address 1040, and the instruction
after overflow is an LDCL at address 1040. This case may be
difficult to detect by the user, although it is possible for tools to
be able to detect this because the target address of a branch is
always traced, even if the next instruction is not.
■ The amount of data trace lost depends on the position of the next
indirect branch, and the data tracing mode selected. An indirect
branch is any branch which is not a B, BL or BLX instruction, such as
an LDR to the program counter.
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