EPXA4 Datasheet, PDF (12/34 Pages) Altera Corporation – Excalibur Devices

Errata Sheet - Appendix A
Table 3. Minimum length of the wait-state period for the problem to occur
ETM Configuration FIFO size Minimum FIFO Port size Cycles to Minimum number of
depth at overflow
drain FIFO consecutive wait states
Large
Medium
Small
45 bytes
37 bytes
18 bytes
10 bytes
9 bytes
1 byte
16-bit
19
20
8-bit
37
38
4-bit
74
75
16-bit
5
6
8-bit
10
11
4-bit
20
21
8-bit
1
2
4-bit
2
3
While the minimum number of consecutive wait states required for this
erratum to occur is increased by reducing the port size, a wider port size
is still recommended as a more narrow port size will cause overflows to
occur more frequently.
These cycle calculations are based on having eight free bytes in the FIFO
when nine bytes are generated in a cycle. This occurs for the first data
transfer after trace has been turned on, and requires both data value and
data address tracing to be enabled. Most overflows will require a longer
wait-state than this.
The ETM FIFOFULL signal attempts to preemptively insert processor
wait states to prevent the FIFO from overflowing. Consequently, this
means that this erratum will occur more often when FIFOFULL is
enabled. In this case this erratum interacts with a separate category 3
erratum, “FIFOFULL LOW for one cycle during overflow—Category 3”,
documented on page 25. This causes FIFOFULL to be low for the first
cycle of overflow, during which the ETM will not cause the processor to
stall. As a result, while enabling FIFOFULL can increase the chance of this
erratum occurring, it does not on its own cause the erratum to occur,
because a wait-state must occur at the same time that FIFOFULL goes low
for this one cycle.
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