EPXA4 Datasheet, PDF (5/34 Pages) Altera Corporation – Excalibur Devices

Excalibur EPXA4 Devices Errata Sheet
UART
This section provides further information about errata in the UART.
4.1 UART State Undefined Following Reset
When the device comes out of reset, the UART may sometimes generate a
modem interrupt and behave as though a character has been received.
SDRAM
Work Around
To avoid generating a modem interrupt, clear all interrupts and flush the
receive and transmit FIFO buffers before interrupts from the UART are
enabled.
This section provides further information about errata in the SDRAM.
5.1 32-bit DDR SDRAM Memories are Not Supported
The SDRAM controller in the ARM-based family (including the EPXA4)
does not support interfacing with 32-bit DDR SDRAM devices that use the
A8 address line for the command sequence. Also 32-bit DDR memories
have one DQS pin; ARM-based devices require four (one per byte).
Memories that use the A10 address line for the command sequence and
have one DQS pin per byte are supported.
5.2 Improper DDR SDRAM Data Accesses for Certain Clock Ratios
Incorrect data may result from DDR SDRAM accesses if the AHB1 or
AHB2 master clock is greater than 4 times faster than the SDRAM clock,
SD_CLK.
Embedded
Trace Module
Version 2a
Work Around
Ensure that the AHB1/2 clock frequency is less than or equal to 4 times the
SDRAM clock frequency.
EPXA4 devices include the ARM ETM9 version 2a. Please see the
ETM9_Rev_2a_Errata.doc for errata on this version of the ETM9. This
document is available on the ARM Limited website.
Version 2a has a different configuration code register value compared to
version 1, which is used in the EPXA10 devices. The ARM Trace Tools
version 1.1 does not support ETM9 version 2a. Support will be included
in a new version of the trace tools planned for Q2 2002.
Altera Corporation
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