EPXA4 Datasheet, PDF (10/34 Pages) Altera Corporation – Excalibur Devices

Errata Sheet - Appendix A
Table 2. Example of invalid data trace following overflow during wait-state period
Address
Instruction
Data trace Instruction Data transfer
entering flow reported reported by ETM
ETM FIFO^a by ETM
Notes
1004
LDMIA r6, {r0 – r4} [r6]
[r6+1]
[r6+2]
[r6+3]
[r6+4]
1008
LDR r7, [r8]
[r8]
1004 with data
Overflow
1004 with data
1008 with data
r0 <= [r6]
r1 <= [r6+1]
r2 <= [r6+2]
r0 <= [r6+3]
r1 <= [r6+4]
r2 <= [r8]^b
r3 <= invalid data^b
r4 <= invalid data^b
r7 <= invalid data^b
ETM begins to log the data transferred
from the contents of r6 to each registers
in the list in turn, with r6 post-
incremented each time.
Wait-state begins, stalling data
transfers.
Overflow occurs (due to data trace
continuing to enter the FIFO from the
ETM’s internal pipeline) causing tracing
to be suspended
FIFO drains and overflow clears
Wait-state ends and data transfers
resume
The instruction is reported once more by
ETM as trace restarts, data trace
resumes and now incorrect data values
are reported.
The required operation was that no data
should enter the FIFO at this point, as
there is no way to indicate which
transfers were traced.
The ETM now also reports an incorrect
data value for register r7
The required operation was that the next
operation after overflow would receive
correct data trace. So, in this example:
r7 <= [r8]
Notes:
(a) Corresponds to data transferred by the core
(b) Data from a future instruction
Note that, in this example, all the data transfers were reported either
before or after the overflow. However, this may not necessarily be the
case, and some transfers before the overflow, and the instruction itself,
may not be reported,
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