EPXA4 Datasheet, PDF (14/34 Pages) Altera Corporation – Excalibur Devices

Errata Sheet - Appendix A
One of the following apply:
The first instruction traced following the overflow is an indirect branch.
The data (addresses and values) traced with this instruction must be
treated as invalid, but data traced for other instructions will be
unaffected. It is always possible for invalid trace to be detected by the
tools when the first instruction is an indirect branch, except in the
case of an SWPB instruction when a 16-bit trace port is in use. If you
are using tools which detect this, such as ARM’s Trace Debug Tools,
the data trace can be treated as valid if the first instruction following
the overflow is an indirect branch and no error has been detected.
The next instruction to have data traced does not occur until after the next
indirect branch.
The data traced with the first instruction must be treated as invalid,
but data traced for future instructions is unaffected. It is not always
possible for the tools to detect the error.
Other instructions have data traced before the next indirect branch, and only data
addresses are being traced.
The data addresses must be treated as invalid for the first instruction,
but will be valid for the instructions which follow.
Another instruction has data traced before the next indirect branch, and either
only data values are being traced, or the first instruction following the overflow
is an MRRC or MCRR.
The data values traced with all the instructions up to the next indirect
branch must be treated as invalid. Data values traced after the next
indirect branch are unaffected by this erratum and will be valid
Another instruction has data traced before the next indirect branch, and data
values and addresses are both being traced.
The data values and addresses traced with all instructions before the
next indirect branch must be treated as invalid. Data addresses traced
for instructions after the next indirect branch, but before the next full
32-bit data address, must also be treated as invalid. The first data
address output after each trace gap is a full 32-bit address, after which
a full data address is forced if one has not been output for 1024 cycles.
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