EPXA4 Datasheet, PDF (24/34 Pages) Altera Corporation – Excalibur Devices

Errata Sheet - Appendix A
It is therefore possible to determine where external stall cycles have been
inserted, and to count forward 6 cycles from that point to find where they
should have been inserted, not counting other external stall cycles. This is
a complex procedure which cannot easily be automated, and cannot be
regarded as a complete workaround.
Table 7 shows an example of this technique. Note that, as in Table 6, the
trace reports stall cycles before the corresponding instruction is traced, not
after.
Table 7. Example of how to calculate the correct location of a stall (Part 1 of 2)
Cycle Address Instruction
600
2000
601
2004
602
603
2008
604
200C
605
606
607
2018
608
201C
609
610
2020
611
2024
MOV r1,r0
LDR r2,var0
(interlock on r2)
ADD r2,r2,#1
B 2018
(Branch delay)
(Branch delay)
ADD r2,r2,#1
LDR r3,var1
(LDR stalled)
LDR r4,var2
ADD r2,r2,#1
612
613
614
615
616
617
Actual trace Reconstructed
trace
Notes
This is an internal stall and can
be predicted
These cycles are also
predictable internal stalls
IE (instruction
IE for 2000
executed) for 2000
WT (wait)
WT
WT
IE for 2004
IE for 2008
WT
WT
IE for 200C
IE for 2004
IE for 2008
WT
WT
IE for 200C
IE for 2018
An external stall
Only one stall was predicted for 2004.
One must be an external stall.
Counting forward 6 from the first puts
it on 2018, the second on 201C.
Remove it and try to place later.
The stall could correspond to 2018 in
theory, but in this system only the
memory system can cause external
stalls, and the code is in fast
instruction memory, so an ADD could
not cause an external stall.
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