1GB-DDR3L-AS4C128M8D3L Datasheet, PDF (83/88 Pages) Alliance Semiconductor Corporation – internal banks for concurrent operation

1Gb DDR3L – AS4C128M8D3L
Figure 68. Dynamic ODT: Behavior without write command, AL = 0, CWL = 5
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK#
CK
COMMAND
ADDRESS
ODT
RTT
DQS, DQS#
DQ
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
ODTH4
ODTLon
t_AON(min)
t_AON(max)
ODTLoff
RTT_NOM
t_ADC(min)
t_ADC(max)
NOTES:
1. ODTH4 is defined from ODT registered high to ODT registered low, so in this example, ODTH4 is satisfied.
2. ODT registered low at T5 would also be legal.
TRANSITIONING DATA
Don't Care
Figure 69. Dynamic ODT: Behavior with ODT pin being asserted together with write
command for a duration of 6 clock cycles
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK#
CK
COMMAND
ADDRESS
ODT
RTT
NOP
WRS8
VALID
NOP
NOP
ODTLcnw
NOP
NOP
ODTH8
ODTLon
t_AON(min)
ODTLcwn8
t_ADC(max)
NOP
NOP
NOP
NOP
ODTLoff
RTT_WR
NOP
NOP
t_AOF(min)
t_AOF(max)
DQS, DQS#
DQ
WL
Din
Din
Din
Din
Din
Din
Din
Din
b
b+1
b+2
b+3
b+4
b+5
b+6
b+7
NOTES:
Example for BL8 (via MRS or OTF), AL = 0, CWL = 5. In this example, ODTH8 = 6 is exactly satisfied.
TRANSITIONING DATA
Don't Care
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Rev. 2.0
Aug. /2014