1GB-DDR3L-AS4C128M8D3L Datasheet, PDF (30/88 Pages) Alliance Semiconductor Corporation – internal banks for concurrent operation

1Gb DDR3L – AS4C128M8D3L
NOTE 16: tIS(base) and tIH(base) values are for 1V/ns CMD/ADD single-ended slew rate and 2V/ns CK, CK# differential
slew rate. Note for DQ and DM signals, VREF(DC) = VRefDQ(DC). For input only pins except RESET#,
VRef(DC) = VRefCA(DC). See “Address / Command Setup, Hold and Derating”.
NOTE 17: tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, DQS# differential
slew rate. Note for DQ and DM signals, VREF(DC) = VRefDQ(DC). For input only pins except RESET#,
VRef(DC) = VRefCA(DC). See “Data Setup, Hold and Slew Rate Derating”.
NOTE 18: Start of internal write transaction is defined as follows:
- For BL8 (fixed by MRS and on- the-fly): Rising clock edge 4 clock cycles after WL.
- For BC4 (on- the- fly): Rising clock edge 4 clock cycles after WL.
- For BC4 (fixed by MRS): Rising clock edge 2 clock cycles after WL.
NOTE 19: The maximum read preamble is bound by tLZ(DQS)min on the left side and tDQSCK(max) on the right side. See
“Clock to Data Strobe Relationship”.
NOTE 20: CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh
are in progress, but power-down IDD spec will not be applied until finishing those operations.
NOTE 21: Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is satisfied,
there are cases where additional time such as tXPDLL(min) is also required. See “Power-Down clarifications-Case
2”.
NOTE 22: Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.
NOTE 23: One ZQCS command can effectively correct a minimum of 0.5 % (ZQ Correction) of RON and RTT impedance
error within 64 nCK for all speed bins assuming the maximum sensitivities specified in the ‘Output Driver Voltage
and Temperature Sensitivity’ and ‘ODT Voltage and Temperature Sensitivity’ tables. The appropriate interval
between ZQCS commands can be determined from these tables and other application-specific parameters. One
method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage
(Vdriftrate) drift rates that the SDRAM is subject to in the application, is illustrated. The interval could be defined
by
the following formula:
ZQCorrection
(TSens × Tdriftrate) + (VSens × Vdriftrate)
where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM temperature
and voltage sensitivities.
For example, if TSens = 1.5% / oC, VSens = 0.15% / mV, Tdriftrate = 1 oC / sec and Vdriftrate = 15 mV / sec, then
the interval between ZQCS commands is calculated as:
0.5
= 0.133 128ms
(1.5 × 1) + (0.15 × 15)
NOTE 24: n = from 13 cycles to 50 cycles. This row defines 38 parameters.
NOTE 25: tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following
falling edge.
NOTE 26: tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following
rising edge.
NOTE 27: The tIS(base) AC135 specifications are adjusted from the tIS(base) specification by adding an additional 100 ps
of derating to accommodate for the lower alternate threshold of 135 mV and another 25 ps to account for the
earlier reference point [(160 mv - 135 mV) / 1 V/ns].
NOTE 28: Pulse width of a input signal is defined as the width between the first crossing of Vref(dc) and the consecutive
crossing of Vref(dc).
NOTE 29: tDQSL describes the instantaneous differential input low pulse width on DQS - DQS#, as measured from one
falling edge to the next consecutive rising edge.
NOTE 30: tDQSH describes the instantaneous differential input high pulse width on DQS - DQS#, as measured from one
rising edge to the next consecutive falling edge.
NOTE 31: tDQSH,act + tDQSL,act = 1 tCK,act ; with tXYZ,act being the actual measured value of the respective timing
parameter in the application.
NOTE 32: tDSH,act + tDSS,act = 1 tCK,act ; with tXYZ,act being the actual measured value of the respective timing
parameter in the application.
NOTE 33: The CL and CWL settings result in tCK requirements. When making a selection of tCK, both CL and CWL
requirement settings need to be fulfilled.
Confidential
30
Rev. 2.0
Aug. /2014