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1GB-DDR3L-AS4C128M8D3L Datasheet, PDF (26/88 Pages) Alliance Semiconductor Corporation – internal banks for concurrent operation
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1Gb DDR3L – AS4C128M8D3L
Table 18. Electrical Characteristics and Recommended A.C. Operating Conditions
(VDD = 1.35V)
Symbol
Parameter
tAA
tRCD
tRP
tRC
tRAS
tCK(avg)
tCK (DLL_OFF)
tCH(avg)
tCL(avg)
tDQSQ
tQH
tLZ(DQ)
tHZ(DQ)
tDS(base)
tDH(base)
tDIPW
tRPRE
tRPST
tQSH
tQSL
tWPRE
tWPST
tDQSCK
tLZ(DQS)
tHZ(DQS)
Internal read command to first data
ACT to internal read or write delay time
PRE command period
ACT to ACT or REF command period
ACTIVE to PRECHARGE command period
CL=5, CWL=5
CL=6, CWL=5
CL=7, CWL=6
Average clock period
CL=8, CWL=6
CL=9, CWL=7
CL=10, CWL=7
CL=11, CWL=8
Minimum Clock Cycle Time (DLL off mode)
Average clock HIGH pulse width
Average Clock LOW pulse width
DQS, DQS# to DQ skew, per group, per access
DQ output hold time from DQS, DQS#
DQ low-impedance time from CK, CK#
DQ high impedance time from CK, CK#
Data setup time to DQS, DQS#
referenced to Vih(ac) / Vil(ac) levels
AC135
Data hold time from DQS, DQS#
referenced to Vih(dc) / Vil(dc) levels
DC90
DQ and DM Input pulse width for each input
DQS,DQS# differential READ Preamble
DQS, DQS# differential READ Postamble
DQS, DQS# differential output high time
DQS, DQS# differential output low time
DQS, DQS# differential WRITE Preamble
DQS, DQS# differential WRITE Postamble
DQS, DQS# rising edge output access
time from rising CK, CK#
DQS and DQS# low-impedance time
(Referenced from RL - 1)
DQS and DQS# high-impedance time
(Referenced from RL + BL/2)
tDQSL
DQS, DQS# differential input low pulse width
Min.
13.75
13.75
13.75
48.75
35
3.0
2.5
1.875
1.875
1.5
1.5
1.25
8
0.47
0.47
-
0.38
-450
-
25
55
360
0.9
0.3
0.4
0.4
0.9
0.3
-225
-450
-
0.45
-12
Max.
20
-
-
-
9 * tREFI
<3.3
<3.3
<2.5
<2.5
<1.875
<1.875
<1. 5
-
0.53
0.53
100
-
225
225
-
-
-
-
-
-
-
-
-
225
225
225
0.55
tDQSH
tDQSS
tDSS
tDSH
tDLLK
DQS, DQS# differential input high pulse width
DQS, DQS# rising edge to CK, CK# rising edge
DQS, DQS# falling edge setup time to
CK, CK# rising edge
DQS, DQS# falling edge hold time from
CK, CK# rising edge
DLL locking time
0.45
-0.27
0.18
0.18
512
0.55
0.27
-
-
-
Unit Note
ns
ns
ns
ns
ns
ns
ns
ns 33
ns 33
ns 33
ns 33
ns 33
ns 6
tCK
tCK
ps 13
tCK 13
ps 13,14
ps 13,14
ps 17
ps 17
ps
tCK 13,19
tCK 11,13
tCK 13
tCK 13
tCK
1
tCK
1
ps 13
ps
13,
14
ps
13,
14
tCK
29,
31
tCK
30,
31
tCK
tCK 32
tCK 32
tCK
Confidential
26
Rev. 2.0
Aug. /2014
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