1GB-DDR3L-AS4C128M8D3L Datasheet, PDF(41/88 Page) Alliance Semiconductor Corporation

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1GB-DDR3L-AS4C128M8D3L Datasheet, PDF (41/88 Pages) Alliance Semiconductor Corporation – internal banks for concurrent operation

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1Gb DDR3L â AS4C128M8D3L

Figure14. Timing details of Write Leveling sequence

(DQS â DQS# is capturing CK â CK# low at T1 and CK â CK# high at T2)

Notes 5

CK#

T1 tWLH

tWLS

tWLH

Notes 1

Notes 2

COMMAND

MRS

NOP

tMOD

NOP

ODT

Notes 4

Diff_DQS

One Prime DQ:

Notes 3

Prime DQ

tWLDQSEN

tWLMRD

Notes 6

tDQSL

Notes 6

tDQSH

tWLO

Notes 6

tDQSL

t Notes 6

DQSH

tWLO

Late Remaining DQs

Early Remaining DQs

All DQs are Prime:

Notes 3

Late Prime DQs

Notes 3

Early Prime DQs

tWLMRD

tWLO

tWLOE

tWLO

tWLOE

NOTES

tWLO

tWLOE

1. MRS: Load MR1 to enter write leveling mode.

2. NOP: NOP or Deselect.

UNDEFINED Driving MODE TIME BREAK

Don't Care

3. DRAM has the option to drive leveling feedback on a prime DQ or all DQs. If feedback is driven only on one DQ, the remaining DQs must be driven low, as shown in above Figure,

and maintained at this state through out the leveling procedure.

4. diff_DQS is the differential data strobe (DQS, DQS#). Timing reference points are the zero crossings. DQS is shown with solid line, DQS# is shown with dotted line.

5. CK, CK# : CK is shown with solid dark line, where as CK# is drawn with dotted line.

6. DQS, DQS# needs to fulfill minimum pulse width requirements tDQSH(min) and tDQSL(min) as defined for regular Writes; the max pulse width is system dependent.

Confidential

Rev. 2.0

Aug. /2014

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