1GB-DDR3L-AS4C128M8D3L Datasheet, PDF (61/88 Pages) Alliance Semiconductor Corporation – internal banks for concurrent operation

1Gb DDR3L – AS4C128M8D3L
- Address / Command Setup, Hold and Derating
For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet
tIS(base) and tIH(base) and tIH(base) value to the delta tIS and delta tIH derating value respectively.
Example: tIS (total setup time) = tIS(base) + delta tIS.
Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vref(dc) and
the first crossing of VIH(ac)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between
the last crossing of Vref(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the
nominal slew rate line between shaded ‘Vref(dc) to ac region’, use nominal slew rate for derating value. If the actual
signal is later than the nominal slew rate line anywhere between shaded ‘Vref(dc) to ac region’, the slew rate of the
tangent line to the actual signal from the ac level to dc level is used for derating value.
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max
and the first crossing of Vref(dc). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between
the last crossing of VIH(dc)min and the first crossing of Vref(dc). If the actual signal is always later than the nominal
slew rate line between shaded ‘dc to Vref(dc) region’, use nominal slew rate for derating value. If the actual signal is
earlier than the nominal slew rate line anywhere between shaded ‘dc to Vref(dc) region’, the slew rate of a tangent
line to the actual signal from the dc level to Vref(dc) level is used for derating value. For a valid transition the input
signal has to remain above/below VIH/IL(ac) for some time tVAC. Although for slow slew rates the total setup time
might be negative (i.e. a valid input signal will not have reached VIH/IL(ac) at the time of the rising clock transition) a
valid input signal is still required to complete the transition and reach VIH/IL(ac).
Table 40. ADD/CMD Setup and Hold Base-Values for 1V/ns
Symbol
Reference
-12 Unit
t_IS(base) AC160
V_IH/L(ac)
65
ps
t_IS(base) AC135
V_IH/L(ac)
185
ps
t_IH(base) DC90
V_IH/L(dc)
130
ps
NOTE 1: (ac/dc referenced for 1V/ns Address/Command slew rate and 2 V/ns differential CK-CK# slew rate)
NOTE 2: The tIS(base) AC135 specifications are adjusted from the tIS(base) specification by adding an additional 100ps of
derating to accommodate for the lower alternate threshold of 135 mV and another 25 ps to account for the earlier reference
point [(160 mv - 135 mV) / 1 V/ns].
Table 41. Derating values DDR3L-1600 tIS/tIH – (AC160)
CMD 2.0
/ADD _1.5
Slew _1.0
Rate
V/ns
0.9
0.8
0.7
0.6
0.5
0.4
4.0 V/ns
△tIS △tIH
80 45
53 30
0
0
-1
-3
-3
-8
-5 -13
-8 -20
-20 -30
-40 -45
3.0 V/ns
△tIS △tIH
80 45
53 30
0
0
-1
-3
-3
-8
-5 -13
-8 -20
-20 -30
-40 -45
△t_IS, △t_IH derating in [ps] AC/DC based
CK, CK# Differential Slew Rate
2.0 V/ns
△tIS △tIH
1.8 V/ns
△tIS △tIH
1.6 V/ns
△tIS △tIH
80 45 88 53 96 61
53 30 61 38 69 46
0
0
8
8
16 16
-1
-3
7
5
15 13
-3
-8
5
1
13
9
-5 -13
3
-5
11
3
-8 -20
0
-12
8
-4
-20 -30 -12 -22 -4 -14
-40 -45 -32 -37 -24 -29
1.4 V/ns
△tIS △tIH
104 69
77 54
24 24
23 21
21 17
19 11
16
4
4
-6
-16 -21
1.2 V/ns
△tIS △tIH
112 79
85 64
32 34
31 31
29 27
27 21
24 14
12
4
-8 -11
1.0 V/ns
△tIS △tIH
120 95
93 80
40 50
39 47
37 43
35 37
32 30
20 20
0
5
Confidential
61
Rev. 2.0
Aug. /2014