1GB-DDR3L-AS4C128M8D3L Datasheet, PDF (42/88 Pages) Alliance Semiconductor Corporation – internal banks for concurrent operation

1Gb DDR3L – AS4C128M8D3L
 Write Leveling Mode Exit
The following sequence describes how Write Leveling Mode should be exited:
1. After the last rising strobe edge (see ~T0), stop driving the strobe signals (see ~Tc0). Note: From now on, DQ
pins are in undefined driving mode, and will remain undefined, until tMOD after the respective MR command
(Te1).
2. Drive ODT pin low (tIS must be satisfied) and keep it low (see Tb0).
3. After the RTT is switched off, disable Write Level Mode via MRS command (see Tc2).
4. After tMOD is satisfied (Te1), any valid command may be registered. (MR commands may be issued after
tMRD (Td1).
Figure 15. Timing details of Write Leveling exit
CK#
T0
T1
T2
Ta0
Tb0
Tc0
Tc1
Tc2
Td0
Td1
Te0
Te1
CK
COMMAND
NOP
ADDRESS
ODT
RTT_DQS_DQS#
DQS_DQS#
NOP
NOP
NOP
NOP
NOP
NOP
RTT_NOM
t_IS
ODTLoff t_AOFmin
t_AOFmax
MRS
MR1
NOP
t_MRD
VALID
VALID
t_MOD
NOP
VALID
VALID
RTT_DQ
Notes 1
DQ
t_WLO
Result = 1
UNDEFINED Driving MODE
TRANSITIONING TIME BREAK
NOTES:
1. The DQ result = 1 between Ta0 and Tc0 is a result of the DQS, DQS# signals capturing CK high just after the T0 state.
Don't Care
 Extended Temperature Usage
Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3L
SDRAM devices support the following options or requirements referred to in this material:
1. Auto Self-refresh supported
2. Extended Temperature Range supported
3. Double refresh required for operation in the Extended Temperature Range (applies only for devices supporting the
Extended Temperature Range)
 Auto Self-Refresh mode - ASR mode
DDR3L SDRAM provides an Auto-Refresh mode (ASR) for application ease. ASR mode is enabled by setting MR2
bit A6=1 and MR2 bit A7=0. The DRAM will manage Self-Refresh entry in either the Normal or Extended
Temperature Ranges. In this mode, the DRAM will also manage Self-Refresh power consumption when the DRAM
operating temperature changes, lower at low temperatures and higher at high temperatures. If the ASR option is not
supported by DRAM, MR2 bit A6 must set to 0. If the ASR option is not enabled (MR2 bit A6=0), the SRT bit (MR2
bit A7) must be manually programmed with the operating temperature range required during Self-Refresh operation.
Support of the ASR option does not automatically imply support of the Extended Temperature Range.
Confidential
42
Rev. 2.0
Aug. /2014