1GB-DDR3L-AS4C128M8D3L Datasheet, PDF (65/88 Pages) Alliance Semiconductor Corporation – internal banks for concurrent operation

1Gb DDR3L – AS4C128M8D3L
Figure 27. MPR Readout of predefined pattern,BC4 lower nibble then upper nibble
T0
Ta
Tb
Tc0
Tc1
Tc2
Tc3
Tc4
Tc5
Tc6
Tc7
Tc8
Tc9
Tc10
Td
CK#
CK
tMPRR
tMOD
COMMAND
PREA
tRP
MRS
tMOD
READ
READ
t ^{Notes 1}CCD
Notes 1
NOP
NOP
NOP
NOP
NOP
NOP
NOP
MRS
NOP
NOP
VALID
BA
3
VALID
VALID
3
A[1:0]
A[2]
A[9:3]
0
0
0
Notes 2
Notes 2
1
0
1
Notes 3
Notes 4
00
VALID
VALID
VALID
0
00
A10, AP
1
0
VALID
VALID
0
A[11]
0
VALID
VALID
0
A12, BC#
0
VALID
VALID
Notes 1
Notes 1
A[14:13]
0
VALID
VALID
RL
DQS, DQS#
RL
DQ
NOTES:
1. RD with BC4 either by MRS or OTF.
2. Memory Controller must drive 0 on A[1:0].
3. A[2]=0 selects lower 4 nibble bits 0....3.
4. A[2]=1 selects upper 4 nibble bits 4....7.
0
0
TIME BREAK
Don't Care
Figure 28. MPR Readout of predefined pattern,BC4 upper nibble then lower nibble
T0
Ta
Tb
Tc0
Tc1
Tc2
Tc3
Tc4
Tc5
Tc6
Tc7
Tc8
Tc9
Tc10
Td
CK#
CK
tMPRR
tMOD
COMMAND
PREA
tRP
MRS
tMOD
READ
READ
t ^{Notes 1}
Notes 1
CCD
NOP
NOP
NOP
NOP
NOP
NOP
NOP
MRS
NOP
NOP
VALID
BA
3
VALID
VALID
3
A[1:0]
A[2]
A[9:3]
0
0
0
Notes 2
Notes 2
1
1
0
Notes 4
Notes 3
00
VALID
VALID
VALID
0
00
A10, AP
1
0
VALID
VALID
0
A[11]
0
VALID
VALID
0
A12, BC#
0
VALID
VALID
Notes 1
Notes 1
A[14:13]
0
VALID
VALID
RL
DQS, DQS#
RL
DQ
NOTES:
1. RD with BC4 either by MRS or OTF.
2. Memory Controller must drive 0 on A[1:0].
3. A[2]=0 selects lower 4 nibble bits 0....3.
4. A[2]=1 selects upper 4 nibble bits 4....7.
0
0
TIME BREAK
Don't Care
Confidential
65
Rev. 2.0
Aug. /2014