1GB-DDR3L-AS4C128M8D3L Datasheet, PDF (28/88 Pages) Alliance Semiconductor Corporation – internal banks for concurrent operation

1Gb DDR3L – AS4C128M8D3L
t_RDPDEN
Timing of RD/RDA command to Power
Down entry
RL + 4 +
1
-
t_WRPDEN
Timing of WR command to Power Down
entry (BL8OTF, BL8MRS, BC4OTF)
t_WRAPDEN
Timing of WRA command to Power
Down entry (BL8OTF, BL8MRS,BC4OTF)
WL + 4
+
-
(t_WR / t_CK)
WL + 4
+ WR +
-
1
t_WRPDEN
Timing of WR command to Power Down entry
(BC4MRS)
WL + 2
+
(t_WR / t_CK)
-
t_WRAPDEN
Timing of WRA command to Power Down entry
(BC4MRS)
WL + 2
+ WR +
1
-
t_CK
t_CK
9
t_CK 10
t_CK
9
t_CK 10
t_REFPDEN Timing of REF command to Power Down entry
1
-
t_CK
20,
21
t_MRSPDEN
ODTLon
ODTLoff
ODTH4
Timing of MRS command to Power Down entry
ODT turn on Latency
ODT turn off Latency
ODT high time without write command or
with write command and BC4
tMOD(min)
-
WL - 2 = CWL + AL - 2
WL - 2 = CWL + AL - 2 ^tCK
4
-
t_CK
ODTH8
ODT high time with Write command and BL8
6
t_AONPD
Asynchronous RTT turn-on delay (Power- Down
with DLL frozen)
2
t_AOFPD
Asynchronous RTT turn-off delay (Power-
Down with DLL frozen)
2
-
t_CK
8.5
ns
8.5
ns
t_AON
RTT turn-on
t_AOF
RTT_Nom and RTT_WR turn-off time
from ODTLoff reference
-225
0.3
225
ps 7
0.7
t_CK
8
t_ADC
t_WLMRD
t_WLDQSEN
t_WLS
t_WLH
RTT dynamic change skew
First DQS/DQS# rising edge after write
leveling mode is programmed
DQS/DQS# delay after write leveling
mode is programmed
Write leveling setup time from rising CK,
CK# crossing to rising DQS, DQS# crossing
Write leveling hold time from rising DQS,
DQS# crossing to rising CK, CK# crossing
0.3
0.7
t_CK
40
-
t_CK
3
25
-
t_CK
3
165
-
ps
165
-
ps
t_WLO
t_WLOE
t_RFC
t_REFI
Write leveling output delay
0
Write leveling output error
0
REF command to ACT or REF command time
110
-40°C to 85°C -
Average periodic refresh interval
85°C to 95°C
-
7.5
ns
2
ns
-
ns
7.8
μs
3.9
μs
NOTE 1: Actual value dependant upon measurement level.
NOTE 2: Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands.
NOTE 3: The max values are system dependent.
NOTE 4: WR as programmed in mode register.
NOTE 5: Value must be rounded-up to next higher integer value
NOTE 6: There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI.
NOTE 7: For definition of RTT turn-on time tAON See “Timing Parameters”.
NOTE 8: For definition of RTT turn-off time tAOF See “Timing Parameters”.
NOTE 9: tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next integer.
NOTE 10: WR in clock cycles as programmed in MR0.
NOTE 11: The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on
the right side. See “Clock to Data Strobe Relationship”.
Confidential
28
Rev. 2.0
Aug. /2014