1GB-DDR3L-AS4C128M8D3L Datasheet, PDF (72/88 Pages) Alliance Semiconductor Corporation – internal banks for concurrent operation

1Gb DDR3L – AS4C128M8D3L
Figure 43. WRITE(BC4) to READ (BC4) operation
T0
T1
T2
T3
T4
T5
CK#
CK
Notes 3
COMMAND
WRITE
NOP
NOP
NOP
NOP
NOP
Notes 4
ADDRESS
Bank,
Col n
DQS, DQS#
t_WPRE
T6
T7
NOP
NOP
t_WPST
T8
T9
Tn
NOP
NOP
t ^{Notes 5}
WTR
READ
Notes 2
DQ
WL = 5
Din
Din
Din
Din
n
n+1
n+2
n+3
NOTES:
1. BC4, WL = 5, RL = 5.
2. DIN n = data-in from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0[A1:0 = 10] during WRITE command at T0 and READ command at Tn.
5. tWTR controls the write to read delay to the same device and starts with the first rising clock edge after the last write data shown at T7.
TIME BREAK
TRANSITIONING DATA
RL = 5
, ^{Don't Care}
Figure 44. WRITE(BC4) to Precharge Operation
T0
T1
T2
T3
T4
T5
CK#
CK
Notes 3
COMMAND
WRITE
NOP
NOP
NOP
NOP
NOP
Notes 4
ADDRESS
Bank,
Col n
DQS, DQS#
t_WPRE
T6
T7
NOP
NOP
t_WPST
T8
T9
Tn
NOP
NOP
t ^{Notes 5}
WR
PRE
Notes 2
DQ
WL = 5
Din
Din
Din
Din
n
n+1
n+2
n+3
NOTES:
1. BC4, WL = 5, RL = 5.
2. DIN n = data-in from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0[A1:0 = 10] during WRITE command at T0.
5. The write recovery time (tWR) referenced from the first rising clock edge after the last write data shown at T7.
tWR specifies the last burst write cycle until the precharge command can be issued to the same bank .
TIME BREAK
TRANSITIONING DATA
Don't Care
Confidential
72
Rev. 2.0
Aug. /2014