1GB-DDR3L-AS4C128M8D3L Datasheet, PDF (7/88 Pages) Alliance Semiconductor Corporation – internal banks for concurrent operation

1Gb DDR3L – AS4C128M8D3L
DM
DQ0 – DQ7
ODT
RESET#
VDD
VSS
VDDQ
VSSQ
VREFCA
VREFDQ
ZQ
NC
Input Data Input Mask: Input data is masked when DM is sampled HIGH during a write cycle.
DM has an optional use as TDQS on the x8.
Input / Data I/O: The DQ0-DQ7 input and output data are synchronized with positive and negative
Output edges of DQS and DQS#. The I/Os are byte-maskable during Writes.
Input
On Die Termination: ODT (registered HIGH) enables termination resistance internal to
the DDR3L SDRAM. When enabled, ODT is applied to each DQ, DQS, DQS#, DM/TDQS
and TDQS# signal. (When TDQS is enabled via Mode Register A11=1 in MR1) The ODT
pin will be ignored if Mode-registers, MR1and MR2, are programmed to disable RTT.
Input
Active Low Asynchronous Reset: Reset is active when RESET# is LOW, and inactive
when RESET# is HIGH. RESET# must be HIGH during normal operation. RESET# is a
CMOS rail to rail signal with DC high and low at 80% and 20% of VDD
Supply Power Supply: +1.35V -0.067V/ +0.1V
Supply Ground
Supply DQ Power: +1.35V -0.067V/ +0.1V
Supply DQ Ground
Supply Reference voltage for CA
Supply Reference voltage for DQ
Supply Reference pin for ZQ calibration.
- No Connect: These pins should be left unconnected.
Confidential
7
Rev. 2.0
Aug. /2014