1GB-DDR3L-AS4C128M8D3L Datasheet, PDF (29/88 Pages) Alliance Semiconductor Corporation – internal banks for concurrent operation

1Gb DDR3L – AS4C128M8D3L
NOTE 12: Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter,
this parameter needs to be derated by t.b.d.
NOTE 13: Value is only valid for RON34.
NOTE 14: Single ended signal parameter.
NOTE 15: tREFI depends on TOPER.
Confidential
29
Rev. 2.0
Aug. /2014