1GB-DDR3L-AS4C128M8D3L Datasheet, PDF (27/88 Pages) Alliance Semiconductor Corporation – internal banks for concurrent operation

1Gb DDR3L – AS4C128M8D3L
t_RTP
t_WTR
t_WR
t_MRD
t_MOD
t_CCD
t_DAL(min)
t_MPRR
t_RRD
t_FAW
t_IS(base)
t_IH(base)
t_IPW
t_ZQinit
t_ZQoper
t_ZQCS
t_XPR
t_XS
t_XSDLL
t_CKESR
t_CKSRE
t_CKSRX
t_XP
t_XPDLL
t_CKE
t_CPDED
t_PD
t_ACTPDEN
t_PRPDEN
Internal READ Command to
PRECHARGE Command delay
max
(4t_CK,
-
7.5ns)
Delay from start of internal write
transaction to internal read command
max
(4t_CK,
-
7.5ns)
WRITE recovery time
15
-
Mode Register Set command cycle time
4
-
Mode Register Set command update delay
max
12t_CK,
-
15ns)
CAS# to CAS# command delay
4
-
Auto precharge write recovery + prechargetime
WR + t_RP
Multi-Purpose Register Recovery Time
1
-
ACTIVE to ACTIVE command period
max
(4t_CK,
-
6ns)
Four activate window
30
-
Command and Address setup time to CK,
AC160 60
-
CK# referenced to Vih(ac) / Vil(ac) levels
AC135 185
-
Command and Address hold time from CK,
CK# referenced to Vih(dc) / Vil(dc) levels
DC90
130
-
Control and Address Input pulse width for each
input
560
-
Power-up and RESET calibration time
512
-
Normal operation Full calibration time
256
-
Normal operation Short calibration time
64
-
max(5t_CK,
Exit Reset from CKE HIGH to a valid command t_RFC(min) +
-
10ns)
Exit Self Refresh to commands not
requiring a locked DLL
max(5t_CK,
t_RFC(min) +
-
10ns)
Exit Self Refresh to commands requiring a
locked DLL
tDLLK_(min)
-
Minimum CKE low width for Self Refresh
entry to exit timing
tCKE_(min)
+ 1t_CK
-
Valid Clock Requirement after Self Refresh Entry max(5t_CK,
(SRE) or Power-Down Entry (PDE)
10 ns)
-
Valid Clock Requirement before Self Refresh Exit max(5t_CK,
(SRX) or Power-Down Exit (PDX) or Reset Exit
10 ns)
-
Exit Power Down with DLL on to any valid
command; Exit Precharge Power Down with DLL
frozen to commands not requiring a locked DLL
max(3t_CK,
6 ns)
-
Exit Precharge Power Down with DLL
frozen to commands requiring a lockedDLL
max
(10t_CK,
-
24 ns)
CKE minimum pulse width
max(3t_CK,
5 ns)
-
Command pass disable delay
2
-
Power Down Entry to Exit Timing
Timing of ACT command to Power Down
entry
Timing of PRE or PREA command to
Power Down entry
tCKE_(min)
1
1
9 * t_REFI
-
-
t_CK
t_CK 18
ns 18
t_CK
t_CK
t_CK
t_CK
t_CK 22
t_CK
ns
ps 16
ps 16,27
ps 16
ps 28
t_CK
t_CK
t_CK 23
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
2
t_CK
t_CK
15
t_CK 20
t_CK 20
Confidential
27
Rev. 2.0
Aug. /2014