1GB-DDR3L-AS4C128M8D3L Datasheet, PDF (4/88 Pages) Alliance Semiconductor Corporation – internal banks for concurrent operation

Figure 2. Block Diagram
CK
CK#
CKE
DLL
CLOCK
BUFFER
RESET#
CS#
RAS#
CAS#
WE#
COMMAND
DECODER
A10/AP
A12/BC#
A0-A9
A11
A13
BA0-BA2
COLUMN
COUNTER
ADDRESS
BUFFER
1Gb DDR3L – AS4C128M8D3L
CONTROL
SIGNAL
GENERATOR
MODE
REGISTER
16M x 8
CELL ARRAY
(BANK #0)
Column Decoder
16M x 8
CELL ARRAY
(BANK #1)
Column Decoder
16M x 8
CELL ARRAY
(BANK #2)
Column Decoder
16M x 8
CELL ARRAY
(BANK #3)
Column Decoder
16M x 8
CELL ARRAY
(BANK #4)
Column Decoder
VSSQ
DQS
DQS#
TDQS
TDQS#
Confidential
REFRESH
COUNTER
RZQ
ZQCL
ZQ
ZQCS
CAL
DATA
STROBE
BUFFER
DQ0
DQ7
DQ
Buffer
ODT DM
4
16M x 8
CELL ARRAY
(BANK #5)
Column Decoder
16M x 8
CELL ARRAY
(BANK #6)
Column Decoder
16M x 8
CELL ARRAY
(BANK #7)
Column Decoder
Rev. 2.0
Aug. /2014