1GB-DDR3L-AS4C128M8D3L Datasheet, PDF (23/88 Pages) Alliance Semiconductor Corporation – internal banks for concurrent operation

1Gb DDR3L – AS4C128M8D3L
Table 15. Differential AC and DC Input Levels
Symbol
Parameter
-12
Min.
Max.
Unit Note
VIHdiff
VILdiff
Differential input high
Differential input logic low
0.18
-
V 1, 3
-
- 0.18
V 1, 3
VIHdiff(AC)
Differential input high ac
2 x (VIH(AC) - V_REF)
-
V 2, 3
VILdiff(AC)
Differential input low ac
-
2 x (VIL(AC) - V_REF) V 2, 3
NOTE 1: Used to define a differential signal slew-rate.
NOTE 2: For CK - CK# use VIH/VIL(ac) of ADD/CMD and VREFCA; for DQS, DQS# use VIH/VIL(ac) of DQs and VREFDQ;
if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here.
NOTE 3: These values are not defined; however, the single-ended signals CK, CK#, DQS, DQS# need to be within the
respective limits (VIH(dc) max, VIL(dc)min) for single-ended signals as well as the limitations for overshoot and
undershoot.
Table 16. Capacitance (V_DD = 1.35V, f = 1MHz, T_OPER = 25 C)
Symbol
Parameter
DDR3L-1600
Min. Max.
Input/output capacitance,
CIO
(DQ, DM, DQS, DQS#, TDQS,
TDQS#)
1.5
2.3
CCK
Input capacitance, CK and CK#
0.8
1.4
Unit Note
pF 1, 2, 3
pF 2, 3
CDCK
Input capacitance delta, CK and CK#
0
0.15 pF 2, 3, 4
CDDQS
CI
CDI_CTRL
CDI_ADD_CMD
CDIO
Input/output capacitance delta,
DQS and DQS#
Input capacitance,
(CTRL, ADD, CMD input-only pins)
Input capacitance delta,
(All CTRL input-only pins)
Input capacitance delta,
(All ADD, CMD input-only pins)
Input/output capacitance delta,
(DQ, DM, DQS, DQS#, TDQS,
TDQS#)
0
0.75
-0.4
-0.4
-0.5
0.15 pF 2, 3, 5
1.3
pF 2, 3, 6
0.2
pF
2, 3, 7,
8
0.4
pF
2, 3, 9,
10
0.3
pF 2, 3, 11
CZQ
Input/output capacitance of ZQ pin
-
3
pF 2, 3, 12
NOTE 1: Although the DM, TDQS and TDQS# pins have different functions, the loading matches DQ and DQS.
NOTE 2: This parameter is not subject to production test. It is verified by design and characterization. VDD=VDDQ=1.35V,
VBIAS=VDD/2 and on die termination off.
NOTE 3: This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here.
NOTE 4: Absolute value of CCK-CCK#.
NOTE 5: Absolute value of CIO(DQS)-CIO(DQS#).
NOTE 6: CI applies to ODT, CS#, CKE, A0-A13, BA0-BA2, RAS#, CAS#, WE#.
NOTE 7: CDI_CTRL applies to ODT, CS# and CKE.
NOTE 8: CDI_CTRL=CI(CTRL)-0.5*(CI(CK)+CI(CK#)).
NOTE 9: CDI_ADD_CMD applies to A0-A12, BA0-BA2, RAS#, CAS# and WE#.
NOTE 10: CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CK)+CI(CK#)).
NOTE 11: CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO(DQS#)).
NOTE 12: Maximum external load capacitance on ZQ pin: 5 pF.
Confidential
23
Rev. 2.0
Aug. /2014